ZL50111

www.DataSheet4U.com ZL50110/11/14 128, 256 and 1024 Channel CESoP Processors Data Sheet Features General Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchronization recovery across a packet network Grooming capability for Nx64 Kbps trunking ZL50110GAG ZL50111GAG ZL50114GAG October 2005 Ordering Information 552 PBGA 552 PBGA 552 PBGA Trays, Bake & Drypack Trays, Bake & Drypack Trays, Bake & Drypack -40°C to +85°C Direct connection to LIUs, framers, backplanes Dual reference Stratum 3, 4 and 4E DPLL for synchronous operation Circuit Emulation Services Complies with ITU-T recommendation Y.1413 Complies with IETF PWE3 draft standards for CESoPSN and SAToP Complies with CESoP draft IAs for MEF and MFA Structured, synchronous CESoP with clock recovery Unstructured, asynchronous CESoP, with integral per stream clock recovery Network Interfaces Up to 3 x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Ethernet Interfaces System Interfaces Flexible 32 bit host CPU interface (Motorola PowerQUICC™ compatible) On-chip packet memory for self-contained operation, with buffer depths of over 16 ms Up to 8 Mbytes of off-chip packet memory, supporting buffer depths of over 128 ms TDM Interfaces Up to 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports H.110, H-MVIP, ST-BUS backplanes Up to 1024 bi-directional 64 Kbps channels 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports H.110, H-MVIP, ST...