ZL50115

www.DataSheet4U.com ZL50115/16/17/18/19/20 32, 64 and 128 Channel CESoP Processors Data Sheet Features General Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks On chip timing & synchronization recovery across a packet network On chip dual reference Stratum 3 DPLL Grooming capability for Nx64 Kbps trunking Fully compatible with Zarlink's ZL50110, ZL50111 and ZL50114 CESoP processors ZL50115GAG ZL50116GAG ZL50117GAG ZL50118GAG ZL50119GAG ZL50120GAG April 2005 Ordering Information 324 324 324 324 324 324 Ball Ball Ball Ball Ball Ball PBGA PBGA PBGA PBGA PBGA PBGA trays, trays, trays, trays, trays, trays, bake bake bake bake bake bake & & & & & & dry dry dry dry dry dry pack pack pack pack pack pack -40°C to +85 °C Up to 128 bi-directional 64 Kbps channels Direct connection to LIUs, framers, backplanes Circuit Emulation Services Complies with ITU-T recommendation Y.1413 Complies with IETF PWE3 draft standards CESoPSN and SAToP Complies with CESoP Implementation Agreements from MEF 8 and MFA 8.0.0 Structured, synchronous CESoP with clock recovery Unstructured, asynchronous CESoP with integral per-stream clock recovery Customer Side Packet Interfaces 100 Mbps MII Fast Ethernet (ZL50118/19/20 only) (may also be used as a second provider side packet interface) Provider Side Packet Interfaces 100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet Customer Side TDM Interfaces Up to 4 T1/E1, 1 J...