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C3430
Typical Applications
Base Stations
FCXO
Features
Surface Mount Package Reflow Process Compatible Low Phase Noise Build in PLL-Circuit
Output Frequency range Standard frequencies Reference Frequency
Parameter Input frequency Pin 2 Standard input frequencies Min 1 Typ 10 13 26 32,768 Typ
10 MHz – 700 MHz 52; 61.44;104, 122,88 MHz
Max. 160
Parameter Reference Level Reference Input Impedance Harmonics
Min 0.5 2
Max.
-30
Units MHz MHz MHz MHz MHz Units Vpp kΩ dBc
Condition ± 2 ppm
Ordering Code X106 X136 X266 X326 Condition @ 2 kΩ
5
Output Frequency
Parameter output frequency Pin 4 Standard output frequencies Min 10 Typ 52 61.44 Max. 700 Units MHz MHz Condition Ordering Code X526 X616
5
Supply voltage (Vs)
Parameter Supply voltage [Standard] Current consumption Min 3.135 Typ 3.3 Max. 3.465 50 Units VDC mA Condition Ordering Code SV033
5
steady state @ +25°C & 3.3VDC
RF output
Parameter Signal [Standard] Load Signal Level (Vol) Signal Level (Voh) Rise and Fall time Duty cycle Min Typ HCMOS 15 0.3 3.0 40 5 60 pF VDC VDC ns % with Vs=3.3V and 15pF load with Vs=3.3V and 15pF load @ (Voh-Vol)/2 Max. Units Condition Ordering Code RFH
5
Additional parameters
Parameter 3 Phase Noise Min Typ -80 -110 -135 -150 -155 Max. Units dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 10 100 1 10 100 Condition Hz @ 61.44 MHz Hz kHz kHz kHz
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v.2005-10-28 · page 1 of 6 Vectron Asia Pacific Sales Office 1F-2F, No 8 Workshop, No 308 Fenju Road, WaiGaoQiao Free Trade Zone, Pudong, Shanghai, P.R. China 200131 +86 21 5048 0777 tel. +86 21 5048 1881 fax
C3430
FCXO
Additional parameters
Parameter VCXO Control PIN 7 Weight Processing & Packing Operating temperature range Operable temperature range Storage temperature range Min 0.5 Max. 2.5 9 Handling & processing note +70 +85 +125 Typ Units V g °C °C Condition
-20 -30 -55
Enclosures Type G194
Package Codes: Code Height “H” A1 5.9 Pin Length “L” NA
Dimensions: mm
Pin Connections
1 2
Description
Test output of the control voltage for the VCXO (0.5V to 2.8V) Only for modul test or observance Test output signal for PLL lock detected. Low signal à PLL out of lock High signal à PLL in lock Only for modul test or observance Ground connection. Keep traces physically short and connect immediately to ground plane for best performance RF syncronised output. High stabel input frequency for syncronisation, This input is AC coupled, so an external blocking capacitor is not necessary. Power supply pin. External low frequency bypass capacitor should be connected
VCXO Control Lock Detector Output
6;6;9 8 13 14
.