Dual UART. NS16C2552 Datasheet

NS16C2552 UART. Datasheet pdf. Equivalent

NS16C2552 Datasheet
Recommendation NS16C2552 Datasheet
Part NS16C2552
Description (NS16C2552 / NS16C2752) Dual UART
Feature NS16C2552; www.DataSheet4U.com NS16C2552/NS16C2752 Dual UART with 16-byte/64-byte FIFO’s and up to 5 Mbit/s Da.
Manufacture National Semiconductor
Datasheet
Download NS16C2552 Datasheet




National Semiconductor NS16C2552
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PRELIMINARY
August 2006
NS16C2552/NS16C2752
Dual UART with 16-byte/64-byte FIFO’s and up to
5 Mbit/s Data Rate
1.0 General Description
The NS16C2552 and NS16C2752 are dual channel Univer-
sal Asynchronous Receiver/Transmitter (DUART). The foot-
print and the functions are compatible to the PC16552D,
while new features are added to the UART device. These
features include low voltage support, 5V tolerant inputs,
enhanced features, enhanced register set, and higher data
rate.
The two serial channels are completely independent of each
other, except for a common CPU interface and crystal input.
On power-up both channels are functionally identical to the
PC16552D. Each channel can operate with on-chip transmit-
ter and receiver FIFO’s (in FIFO mode).
In the FIFO mode each channel is capable of buffering 16
bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data
in both the transmitter and receiver. The receiver FIFO also
has additional 3 bits of error data per location. All FIFO
control logic is on-chip to minimize system software over-
head and maximize system efficiency.
To improve the CPU processing bandwidth, the data trans-
fers between the DUART and the CPU can be done using
DMA controller. Signaling for DMA transfers is done through
two pins per channel (TXRDY and RXRDY). The RXRDY
function is multiplexed on one pin with the OUT2 and BAUD-
OUT functions. The configuration is through Alternate Func-
tion Register.
The fundamental function of the UART is converting be-
tween parallel and serial data. Serial-to-parallel conversion
is done on the UART receiver and parallel-to-serial conver-
sion is done on the transmitter. The CPU can read the
complete status of each channel at any time. Status infor-
mation reported includes the type and condition of the trans-
fer operations being performed by the DUART, as well as
any error conditions (parity, overrun, framing, or break inter-
rupt).
The NS16C2552 and NS16C2752 include one program-
mable baud rate generator for each channel. Each baud rate
generator is capable of dividing the clock input by divisors of
1 to (216 - 1), and producing a 16X clock for driving the
internal transmitter logic and for receiver sampling circuitry.
The NS16C2552 and NS16C2752 have complete MODEM-
control capability, and a processor-interrupt system. The
interrupts can be programmed by the user to minimize the
processing required to handle the communications link.
2.0 Features
n Dual independent UART
n Up to 5 Mbits/s data transfer rate
n 2.97 V to 5.50 V operational Vcc
n 5 V tolerant I/Os in the entire supply voltage range
n Industrial Temperature: -40˚C to 85˚C
n Default registers are identical to the PC16552D
n NS16C2552/NS16C2752 is pin-to-pin compatible to
NSC PC16552D, EXAR ST16C2552, XR16C2552, XR
16L2552, and Phillips SC16C2552B
n NS16C2752 is compatible to EXAR XR16L2752, and
register compatible to Phillips SC16C752
n Auto Hardware Flow Control (Auto-CTS, Auto-RTS)
n Auto Software Flow Control (Xon, Xoff, and Xon-any)
n Fully programmable character length (5, 6, 7, or 8) with
even, odd, or no parity, stop bit
n Adds or deletes standard asynchronous communication
bits (start, stop, and parity) to or from the serial data
n Independently controlled and prioritized transmit and
receive interrupts
n Complete line status reporting capabilities
n Line break generation and detection
n Internal diagnostic capabilities
— Loopback controls for communications link fault
isolation
— Break, parity, overrun, framing error detection
n Programmable baud generators divide any input clock
by 1 to (216 - 1) and generate the 16 X clock
n IrDA v1.0 wireless Infrared encoder/decoder
n DMA operation (TXRDY/RXRDY)
n Concurrent write to DUART internal register channels 1
and 2
n Multi-function output allows more package functions with
fewer I/O pins
n 44-PLCC or 48-TQFP package
© 2006 National Semiconductor Corporation DS202048
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National Semiconductor NS16C2552
Table of Contents
1.0 General Description ..................................................................................................................................... 1
2.0 Features ....................................................................................................................................................... 1
3.0 System Block Diagram ................................................................................................................................. 4
4.0 Connection Diagrams ................................................................................................................................... 4
5.0 Pin Descriptions ........................................................................................................................................... 5
5.1 PARALLEL BUS INTERFACE ................................................................................................................... 5
5.2 SERIAL IO INTERFACE ............................................................................................................................ 6
5.3 CLOCK AND RESET ................................................................................................................................ 8
5.4 POWER AND GROUND ........................................................................................................................... 8
6.0 Register Set ................................................................................................................................................. 9
6.1 RECEIVE BUFFER REGISTER (RBR) ................................................................................................... 11
6.2 TRANSMIT HOLDING REGISTER (THR) .............................................................................................. 12
6.3 INTERRUPT ENABLE REGISTER (IER) ................................................................................................ 12
6.4 INTERRUPT IDENTIFICATION REGISTER (IIR) ................................................................................... 13
6.5 FIFO CONTROL REGISTER (FCR) ....................................................................................................... 14
6.6 LINE CONTROL REGISTER (LCR) ........................................................................................................ 16
6.7 MODEM CONTROL REGISTER (MCR) ................................................................................................. 18
6.8 LINE STATUS REGISTER (LSR) ............................................................................................................ 20
6.9 MODEM STATUS REGISTER (MSR) ..................................................................................................... 22
6.10 SCRATCHPAD REGISTER (SCR) ........................................................................................................ 23
6.11 PROGRAMMABLE BAUD GENERATOR ............................................................................................. 23
6.12 ALTERNATE FUNCTION REGISTER (AFR) ........................................................................................ 24
6.13 DEVICE IDENTIFICATION REGISTER (ID) ......................................................................................... 24
6.14 ENHANCED FEATURE REGISTER (EFR) .......................................................................................... 25
6.15 SOFTWARE FLOW CONTROL REGISTERS (SFR) ........................................................................... 26
7.0 Operation and Configuration ...................................................................................................................... 27
7.1 CLOCK INPUT ........................................................................................................................................ 27
7.2 RESET ..................................................................................................................................................... 27
7.3 RECEIVER OPERATION ........................................................................................................................ 27
7.3.1 Receive in FIFO Mode ...................................................................................................................... 28
7.3.2 Receive in non-FIFO Mode ............................................................................................................... 28
7.3.3 Receive Hardware Flow Control ........................................................................................................ 29
7.3.4 Receive Flow Control Interrupt .......................................................................................................... 29
7.4 TRANSMIT OPERATION ........................................................................................................................ 29
7.4.1 Transmit in FIFO Mode ...................................................................................................................... 29
7.4.2 Transmit in non-FIFO Mode .............................................................................................................. 30
7.4.3 Transmit Hardware Flow Control ....................................................................................................... 31
7.4.4 Transmit Flow Control Interrupt ......................................................................................................... 31
7.5 SOFTWARE XON/XOFF FLOW CONTROL .......................................................................................... 31
7.6 SPECIAL CHARACTER DETECT .......................................................................................................... 31
7.7 SLEEP MODE ......................................................................................................................................... 32
7.8 INTERNAL LOOPBACK MODE .............................................................................................................. 32
7.9 DMA OPERATION ................................................................................................................................... 32
7.10 INFRARED MODE ................................................................................................................................ 32
8.0 Design Notes .............................................................................................................................................. 34
8.1 DEBUGGING HINTS ............................................................................................................................... 34
8.2 CLOCK FREQUENCY ACCURACY ....................................................................................................... 34
8.3 CRYSTAL REQUIREMENTS .................................................................................................................. 34
8.4 CONFIGURATION EXAMPLES .............................................................................................................. 35
8.4.1 Set Baud Rate ................................................................................................................................... 35
8.4.2 Configure Prescaler Output ............................................................................................................... 35
8.4.3 Set Xon and Xoff flow control ............................................................................................................ 35
8.4.4 Set Software Flow Control ................................................................................................................. 35
8.4.5 Configure Tx/Rx FIFO Threshold ...................................................................................................... 35
8.4.6 Tx and Rx Hardware Flow Control .................................................................................................... 35
8.4.7 Tx and Rx DMA Control .................................................................................................................... 35
8.5 DIFFERENCES BETWEEN THE PC16552D AND NS16C2552/2752 ................................................... 36
8.6 NOTES ON TX FIFO OF NS16C2752 .................................................................................................... 36
9.0 Absolute Maximum Ratings ....................................................................................................................... 37
10.0 DC and AC Specifications ........................................................................................................................ 37
10.1 DC SPECIFICATIONS ........................................................................................................................... 37
10.2 CAPACITANCE ...................................................................................................................................... 37
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National Semiconductor NS16C2552
Table of Contents (Continued)
10.3 AC SPECIFICATIONS ........................................................................................................................... 37
11.0 Timing Diagrams ...................................................................................................................................... 39
12.0 Physical Dimensions ................................................................................................................................ 42
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