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PSD4256G6V
Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY PSD provides an integrated solution to 16-bit MCU-based applications that includes configurable memories, PLD logic, and I/O: s Dual bank Flash memories – 8Mbits of Primary Flash Memory (16 uniform sectors, 64Kbyte) – 512Kbits of Secondary Flash Memory with 4 sectors – Concurrent operation: READ from one memory while erasing and writing the other
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High Endurance: – 100,000 Erase/WRITE Cycles of Flash Memory – 1,000 Erase/WRITE Cycles of PLD – 15 Year Data Retention
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Single Supply Voltage – 3V (+20%/–10%) Memory Speed – 100ns Flash memory and SRAM access time for VCC = 3V (+20%/–10%) – 90ns Flash memory and SRAM access time for VCC = 3.3V (+/–10%)
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256Kbits of SRAM (battery-backed) PLD with Macrocells – Over 3000 Gates of PLD: CPLD and DPLD – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) – DPLD - user defined internal chip select decoding
Figure 1. 80-lead, Thin, Quad, Flat Package
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Seven l/O Ports with 52 I/O pins: 52 individually configurable I/O port pins that can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address output – Special function I/Os – l/O ports may be configured as open-drain outputs
TQFP80 (U)
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In-System Programming (ISP) with JTAG – Built-in JTAG compliant serial port allows fullchip In-System Programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC
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Page Register – Internal page register that can be used to expand the microcontroller address space by a factor of 256
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Programmable power management
1/100
December 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD4256G6V
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PSDsoft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Names (Table 1.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TQFP80 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TQFP80 Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSD Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .