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UT54ACS109 Dataheets PDF



Part Number UT54ACS109
Manufacturers Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology
Description Radiation-Hardened Dual J-K Flip-Flops
Datasheet UT54ACS109 DatasheetUT54ACS109 Datasheet (PDF)

www.DataSheet4U.com UT54ACS109/UT54ACTS109 Radiation-Hardened Dual J-K Flip-Flops FEATURES • • • • • • radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack PINOUTS 16-Pin DIP Top View CLR1 J K1 CLK1 PRE1 Q1 Q1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CLR2 J2 K2 CLK2 PRE2 Q2 Q2 DESCRIPTION The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops..

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www.DataSheet4U.com UT54ACS109/UT54ACTS109 Radiation-Hardened Dual J-K Flip-Flops FEATURES • • • • • • radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack PINOUTS 16-Pin DIP Top View CLR1 J K1 CLK1 PRE1 Q1 Q1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CLR2 J2 K2 CLK2 PRE2 Q2 Q2 DESCRIPTION The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the J and K input can be changed without affecting the levels at the outputs. The flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D flip-flops if J and K are tied together. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS PRE L H L H H H H H CLR H L L H H H H H L CLK X X X J X X X L H L H X K X X X L L H H X OUTPUT Q H L H1 L Q L H H1 H Toggle No Change H L 16-Lead Flatpack Top View CLR1 J1 K1 CLK1 PRE1 Q1 Q1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD CLR2 J2 K2 CLK2 PRE2 Q2 Q2 LOGIC SYMBOL PRE1 J1 CLK1 K1 CLR1 PRE2 J2 CLK2 (5) (2) (4) (3) (1) (11) (14) (12) (9) Q2 (10) Q2 S J1 C1 K1 R (6) Q1 (7) Q1 No Change (13) K2 (15) CLR2 Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum. In addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 61 RadHard MSI Logic UT54ACS109/UT54ACTS109 LOGIC DIAGRAM PRE CLK Q J Q K CLR RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL VDD VI/O TSTG TJ TLS JC PARAMETER Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation LIMIT -0.3 to 7.0 -.3 to VDD +.3 -65 to +150 +175 +300 20 10 1 UNITS V V C C C C/W mA W II PD Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 62 UT54ACS109/UT54ACTS109 RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 UNITS V V C 63 RadHard MSI Logic UT54ACS109/UT54ACTS109 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACTS ACS High-level output voltage 3 ACTS ACS Short-circuit output current 2 ,4 ACTS/ACS Output current10 (Sink) IOH Output current10 (Source) Ptotal IDDQ IDDQ Power dissipation 2, 8 ,9 Quiescent Supply Current Quiescent Supply Current Delta ACTS VIN = VDD or VSS IOL = 8.0mA IOL = 100 A IOH = -8.0mA IOH = -100 A VO = VDD and VSS VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = VDD - 0.4V CL = 50pF VDD = 5.5V For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 Output capacitance 5 = 1MHz @ 0V = 1MHz @ 0V 15 15 pF pF 2.0 10 1.6 mW/ MHz A mA -8 mA .7VDD VDD - 0.25 -200 8 200 .5VDD .7VDD -1 1 CONDITION MIN MAX 0.8 .3VDD UNIT V VIH V IIN VOL A 0.40 0.25 V VOH V IOS IOL mA mA RadHard MSI Logic 64 UT54ACS109/UT54ACTS109 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency shoul.


UPA1552H UT54ACS109 UT54ACTS109


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