LP62S1024B-I

www.DataSheet4U.com LP62S1024B-I Series 128K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0.1 1.0 1.1 1.2 History Initial issue Add 32L Pb-Free TSSOP package type Final version release Change ICCDR1, ICCDR2 (max.) from 3μA to 1μA Add Pb-Free package type for all parts Issue Date May 30, 2002 October 2, 2002 July 18, 2003 June 29, 2004 August 9, 2004 Remark Preliminary Final (August, 2004, Version 1.2) AMIC Technology, Corp. LP62S1024B-I Series 128K X 8 BIT LOW VOLTAGE CMOS SRAM Features „ Power supply range: 2.7V to 3.6V „ Access times: 55/70 ns (max.) „ Current: Very low power version: Operating: 30mA(max.) Standby: 5uA (max.) „ Full static operation, no clock or refreshing required „ All inputs and outputs are directly TTL-compatible „ Common I/O using three-state output „ Output enable and two chip enable inputs for easy application „ Data retention voltage: 2V (min.) „ Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) forward type and 36-pin CSP packages General Description The LP62S1024B-I is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output ena...