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VERSA
Datasheet Rev 1.3
VRS700
VERSA 700: 64kB FLASH, 4kB RAM 23MHz, 3V, 8-Bit MCU
Datasheet Rev 1.3
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
1
VERSA
Datasheet Rev 1.3
VRS700
Overview
The VRS700 is a 3V, 8-bit microcontroller with 64kB of Flash memory and 4K RAM that is based on the architecture of the standard 80C51 microcontroller family. It is pin compatible with these devices. Among the VRS700’s features are 8 PWM outputs, a Watch Dog Timer, bank mapping to permit direct addressing of the 4096 bytes of RAM and a serial port. The VRS700’s hardware features and powerful instruction set make it a versatile and cost-effective controller for a wide range of applications requiring a microcontroller running at 3V. The Flash memory can be programmed using programmers available from Goal Semiconductor or other 3rd party commercial programmers. The VRS700 is available in PLCC-44 and QFP-44 packages in the Industrial Temperature Range.
Features
• • • • • • • • • • • • • • • • • • •
Operating voltage: 3.0V ~ 3.6V General 80C51/80C52 family compatible 64kB on-chip Flash memory 4096 bytes on-chip data RAM Bank mapping direct addressing mode to access RAM Four 8-bit I/O ports + one 4-bit I/O port 8-Channel PWM on P1.0~P1.7 Full duplex serial port (UART) Three 16-bit Timers/Counters Watch Dog Timer 8-bit Unsigned Multiply and Division Instructions BCD arithmetic Direct and Indirect Addressing Two levels of Interrupt Priority and Nested Interrupts Power saving modes Code protection functions Operates at a clock frequency from 3MHz to 23MHz Low EMI (inhibit ALE) Industrial Temperature Range (-40ºC to +85ºC)
FIGURE 2: VRS700 PLCC-44 AND QFP-44 PIN OUT DIAGRAMS
PWM4/P1.4 PWM3/P1.3 PWM2/P1.2 PWM1/T2EX/P1.1 PWM0/T2/P1.0 P4.2 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2
FIGURE 1: VRS700 BLOCK DIAGRAM
8051 PROCESSOR 64kx8 FLASH 4096 Bytes of RAM
ADDRESS/ DATA BUS
PWM5/P1.5
6 7 40 39 1
P0.3/AD3
PORT 0
8
PWM6/P1.6 PWM7/P1.7 RES RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3
PORT 1
8
VRS700 PLCC-44
P0.4/AD4 P0.5/AD5 P0.7/AD7 P0.6/AD6 #EA P4.1 ALE #PSEN P2.7/A15
UART
PORT 2
8
T0/P3.4 T1/P3.5
17 18 28
29
P2.6/A14 P2.5/A13
#WR/P3.6
#RD/P3.7 XTAL2
XTAL1 VSS P4.0 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11
P0.7/AD7 #EA P4.1 ALE P2.7/A15 #PSEN
TIMER 0 TIMER 1 TIMER 2 RESET POWER CONTROL WATCHDOG TIMER
P0.4/AD4
P0.5/AD5 P0.6/AD6
PWM
8
P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P4.2 SPWM0/T2/P1.0 SPWM1/T2EX/P1.1 SPWM2/P1.2 SPWM3/P1.3 SPWM4/P1.4
44 34
33
P2.6/A14 P2.5/A13
23 22
PORT 4
4
P2.4/A12
2 INTERRUPT INPUTS
PORT 3
8
P2.4/A12 P2.3/A11 P2.2/A10
VRS700 QFP-44
P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2
12 11
1
#RD/P3.7 #WR/P3.6
SPWM7/P1.7 RE S RXD/P3.0
SPWM5/P1.5
SPWM6/P1.6
P4.3
TXD/P3.1
#INT0/P3.2
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
#INT1/P3.3
T0/P3.4 T1/P3.5
2
VERSA
Datasheet Rev 1.3
VRS700
Pin Descriptions for QFP-44/PLCC-44
TABLE 1: PIN DESCRIPTIONS FOR QFP-44/PLCC-44
QFP - 44
PLCC - 44
Name
I/O
Function
QFP - 44
PLCC - 44
Name
I/O
Function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
SPWM5 P1.5 SPWM6 P1.6 SPWM7 P1.7 RES RXD P3.0 P4.3 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS P4.0 P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13
O I/O O I/O O I/O I I I/O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O I/O O I/O O I/O O I/O O I/O O I/O O
SPWM Channel 5 Bit 5 of Port 1 SPWM Channel 6 Bit 6 of Port 1 SPWM Channel 7 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Bit 3 of Port 4 Transmit Data & Bit 1 of Port 3 Low True Interrupt 0 Bit 2 of Port 3 Low True Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port 3 Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground Bit 0 of Port 4 Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6
P2.6 A14 P2.7 A15 #PSEN ALE P4.1 #EA P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0. 1 AD1 P0.0 AD0 VDD P4.2 T2 P1.0 SPWM0 T2EX P1.1 SPWM1 P1.2 SPWM2 P1.3 SPWM3 P1.4 SPWM4
I/O O I/O O O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I I/O O I/O O I/O O I/O O
Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable Bit 1 of Port 4 External Access Bit 7 Of Port 0 Data/Add.