WED8L24258V

www.DataSheet4U.com WED8L24258V Asynchronous SRAM, 3.3V, 256Kx24 FEATURES n 256Kx24 bit CMOS Static n Random Access Memory Array • Fast Access Times: 10, 12, and 15ns • Master Output Enable and Write Control • Three Chip Enables for Byte Control • TTL Compatible Inputs and Outputs • Fully Static, No Clocks n Surface Mount Package • 119 Lead BGA (JEDEC MO-163), No. 391 • Small Footprint, 14mmx22mm • Multiple Ground Pins for Maximum Noise Immunity n Single +3.3V (±5%) Supply Operation n DSP Memory Solution • Motorola DSP5630x • Analog Devices SHARCTM The JEDEC Standard 119 lead BGA provides a 69% space savings over using six 256Kx4, 300 mil wide SOJs and the BGA package has a maximum height of 110 mils compared to 148 mils for the SOJ packages. The BGA package also allows the use of the same manufacturing and inspection techniques as the Motorola DSP, which is also in a BGA package. DESCRIPTION The WED8L24258VxxBC is a 3.3V, twelve megabit SRAM constructed with three 256Kx8 die mounted on a multi-layer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V operating voltage, the WED8L24258V is ideal for creating a single chip memory solution for the Motorola DSP5630x or a two chip solution for the Analog Devices SHARCTM DSP. The single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. FIG. 1 1 A B C D E F G H J K L M N P R T...