WED8L24514V

www.DataSheet4U.com WED8L24514V Asynchronous SR AM, 3.3V , 512Kx24 SRAM, 3.3V, FEATURES DESCRIPTION n n 512Kx24 bit CMOS Static Random Access Memory Array Fast Access Times: 10, 12, and 15ns Master Output Enable and Write Control Three Chip Enables for Byte Control TTL Compatible Inputs and Outputs Fully Static, No Clocks The WED8L24514VxxBC is a 3.3V, twelve megabit SRAM constructed with three 512Kx8 die mounted on a multilayer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V operating voltage, the WED8L24514V is ideal for creating a single chip memory solution for the Motorola DSP5630x or a two chip solution for the Analog Devices SHARC TM DSP. The single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. The JEDEC Standard 119 lead BGA provides a 61% space savings over using three 512Kx8, 400 mil wide SOJs and the BGA package has a maximum height of 110 mils compared to 148 mils for the SOJ packages. n Surface Mount Package 119 Lead BGA (JEDEC MO-163), No. 391 Small Footprint, 14mmx22mm Multiple Ground Pins for Maximum Noise Immunity n n Single +3.3V (±5%) Supply Operation DSP Memory Solution Motorola DSP5630x Analog Devices SHARC TM FIG. 1 PIN CONFIGURATION P IN S YMBOLS PIN N AMES 1 A B C D E F G H J K L M N P R T U NC NC I/012 I/013 I/014 I/015 I/016 I/017 NC I/018 I/019 I/020 I/021 I/...