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UJA1061 Dataheets PDF



Part Number UJA1061
Manufacturers NXP
Logo NXP
Description Fault-tolerant CAN/LIN fail-safe system basis chip
Datasheet UJA1061 DatasheetUJA1061 Datasheet (PDF)

UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Rev. 06 — 9 March 2010 Product data sheet 1. General description The UJA1061 fail-safe System Basis Chip (SBC) replaces basic discrete components that are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications that control various power and sensor peripherals by using fault-tolerant CAN as the main netw.

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UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip Rev. 06 — 9 March 2010 Product data sheet 1. General description The UJA1061 fail-safe System Basis Chip (SBC) replaces basic discrete components that are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications that control various power and sensor peripherals by using fault-tolerant CAN as the main network interface and LIN as a local sub-bus. The fail-safe SBC contains the following integrated devices: • ISO11898-3 compliant fault-tolerant CAN transceiver, interoperable with TJA1054, TJA1054A and TJA1055 • LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3 • Advanced independent watchdog • Dedicated voltage regulators for microcontroller and CAN transceiver • Serial peripheral interface (full duplex) • Local wake-up input port • Inhibit/limp-home output port In addition to the advantages of integrating these common ECU functions in a single package, the fail-safe SBC offers an intelligent combination of system-specific functions such as: • Advanced low-power concept • Safe and controlled system start-up behavior • Advanced fail-safe system behavior that prevents any conceivable deadlock • Detailed status reporting on system and subsystem levels The UJA1061 is designed to be used in combination with a microcontroller that incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is always started up in a defined manner. In failure situations, the fail-safe SBC will maintain microcontroller functionality for as long as possible to provide full monitoring and a software-driven fall-back operation. The UJA1061 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures. NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 2. Features and benefits 2.1 General „ Contains a full set of CAN and LIN ECU functions: ‹ CAN transceiver and LIN transceiver ‹ Voltage regulator for the microcontroller (3.3 V or 5.0 V) ‹ Separate voltage regulator for the CAN transceiver (5 V) ‹ Enhanced window watchdog with on-chip oscillator ‹ Serial Peripheral Interface (SPI) for the microcontroller ‹ ECU power management system ‹ Fully integrated autonomous fail-safe system „ Designed for automotive applications: ‹ Supports 14 V, 24 V and 42 V architectures ‹ Excellent ElectroMagnetic Compatibility (EMC) performance ‹ ±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off-board pins ‹ ±6 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins ‹ ±60 V short-circuit proof CAN/LIN-bus pins ‹ Battery and CAN/LIN-bus pins are protected against transients in accordance with ISO 7637 ‹ Very low sleep current „ Supports remote flash programming via the CAN-bus „ Small 6.1 mm × 11 mm HTSSOP32 package with low thermal resistance 2.2 CAN transceiver „ ISO 11898-3 compliant fault-tolerant CAN transceiver „ Enhanced error signalling and reporting „ Dedicated low dropout voltage regulator for the CAN-bus: ‹ Independent from microcontroller supply ‹ Guarded by CAN-bus failure management ‹ Significantly improves EMC performance „ Partial networking option with global wake-up feature, allows selective CAN-bus communication without waking up sleeping nodes „ Bus connections are truly floating when power is off „ Ground shift detection 2.3 LIN transceiver „ LIN 2.0 compliant LIN transceiver „ Enhanced error signalling and reporting „ Downward compatible with LIN 1.3 and the TJA1020 UJA1061_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 9 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 77 NXP Semiconductors UJA1061 Fault-tolerant CAN/LIN fail-safe system basis chip 2.4 Power management „ Smart operating modes and power management modes „ Cyclic wake-up capability in Standby and Sleep modes „ Local wake-up input with cyclic supply feature „ Remote wake-up capability via the CAN-bus and LIN-bus „ External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe) „ 42 V battery-related high-side switch for driving external loads such as relays and wake-up switches „ Intelligent maskable interrupt output 2.5 Fail-safe features „ Safe and predictable behavior under all conditions „ Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision „ Fail-safe coded 16-bit SPI interface for the microcontroller „ Global enable pin for the control of safety-critical hardware „ Detection and detailed reporting of failures: ‹ On-chip oscillator failure and watchdog alerts ‹ Voltage regulator undervoltages ‹ CAN and LIN-bus failures (short-circuits and open-circuit bus wires) ‹ TXD and RXD clamping situations and short-circu.


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