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74AUP1G175 Dataheets PDF



Part Number 74AUP1G175
Manufacturers NXP
Logo NXP
Description Low Power D-Type Flip-Flop
Datasheet 74AUP1G175 Datasheet74AUP1G175 Datasheet (PDF)

www.DataSheet4U.com 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 01 — 15 November 2006 Product data sheet 1. General description The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic p.

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www.DataSheet4U.com 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Rev. 01 — 15 November 2006 Product data sheet 1. General description The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G175 is a single positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C www.DataSheet4U.com NXP Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G175GW 74AUP1G175GM 74AUP1G175GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code aT aT aT Type number 74AUP1G175GW 74AUP1G175GM 74AUP1G175GF 5. Functional diagram 6 3 MR D FF Q 4 CP 001aaa468 1 3 6 CP D MR 001aaa469 1 Q 4 Fig 1. Logic symbol Fig 2. IEC logic symbol CP C C C C Q C D C MR C C C C 001aaa466 Fig 3. Logic diagram 74AUP1G175_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 November 2006 2 of 20 w w w . D a t a S h e e t 4 U . c o m NXP Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 6. Pinning information 6.1 Pinning 74AUP1G175 74AUP1G175 CP CP 1 6 MR GND GND 2 5 VCC D D 3 001aaa467 1 6 MR CP GND 74AUP1G175 1 2 3 6 5 4 MR VCC Q 2 5 VCC 3 4 Q D 4 Q 001aab657 001aae246 Transparent top view Transparent top view Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Symbol CP GND D Q VCC MR Pin description Pin 1 2 3 4 5 6 Description clock input (LOW-to-HIGH, edge-triggered) ground (0 V) data input flip-flop output supply voltage master reset input (active LOW) 7. Functional description Table 4. Function table[1] Input MR Reset (clear) Load ‘1’ Load ‘0’ [1] Operating mode Output CP X ↑ ↑ D X h l Q L H L L H H H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ↑ = LOW-to-HIGH CP transition; X = don’t care. 74AUP1G175_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 November 2006 3 of 20 www.DataSheet4U.com NXP Semiconductors 74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger 8. Limiting values Table 5. Limiting values Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage Conditions VI < 0 V [1] Min −0.5 −0.5 [1] Max +4.6 −50 +4.6 ±50 +4.6 ±20 50 −50 +150 250 Unit V mA V mA V mA mA mA °C mW output clamping current VO > VCC or VO < 0 V output voltage output current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C [2] Active mode and Power-down mode VO = 0 V to VCC −0.5 −65 - The minimum input and output voltage ratings may be exceeded if the in.


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