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74AUP2G38 Dataheets PDF



Part Number 74AUP2G38
Manufacturers NXP
Logo NXP
Description Low Power Dual 2-Input NAND Gate
Datasheet 74AUP2G38 Datasheet74AUP2G38 Datasheet (PDF)

www.DataSheet4U.com 74AUP2G38 Low-power dual 2-input NAND gate (open-drain) Rev. 01 — 16 October 2006 Product data sheet 1. General description The 74AUP2G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption.

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www.DataSheet4U.com 74AUP2G38 Low-power dual 2-input NAND gate (open-drain) Rev. 01 — 16 October 2006 Product data sheet 1. General description The 74AUP2G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output of the device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114-D Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101-C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C www.DataSheet4U.com NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate (open-drain) 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP2G38DC 74AUP2G38GT 74AUP2G38GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C VSSOP8 XSON8 XQFN8 Description Version plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-1 Type number 4. Marking Table 2. Marking Marking code a38 a38 a38 Type number 74AUP2G38DC 74AUP2G38GT 74AUP2G38GM 5. Functional diagram 1 1 2 5 6 1A 1B 2A 2B 1Y 7 2 A 2Y 3 5 6 mnb129 mnb130 & 7 Y & 3 B GND mnb131 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74AUP2G38 1A 1B 2Y GND 1 2 3 4 001aaf547 8 7 6 5 VCC 1Y 2B 2A Fig 4. Pin configuration SOT765-1 (VSSOP8) 74AUP2G38_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 16 October 2006 2 of 16 w w w . D a t a S h e e t 4 U . c o m NXP Semiconductors 74AUP2G38 Low-power dual 2-input NAND gate (open-drain) 74AUP.


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