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74AUP1G0832 Datasheet, Equivalent, AND-OR Gate.

Low Power 3-Input AND-OR Gate

Low Power 3-Input AND-OR Gate

 

 

 

Part 74AUP1G0832
Description Low Power 3-Input AND-OR Gate
Feature www.
DataSheet4U.
com 74AUP1G0832 Low-pow er 3-input AND-OR gate Rev.
01 — 8 No vember 2006 Product data sheet 1.
Gene ral description The 74AUP1G0832 is a hi gh-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs ma kes the circuit tolerant to slower inpu t rise and fall times across the entire VCC range from 0.
8 V to 3.
6 V.
This de vice ensures a very low static and dyna mic power consumption across the entire VCC range from 0.
8 V to 3.
6 V.
This de vice is fully specified for partial po wer-down applicati .
Manufacture NXP
Datasheet
Download 74AUP1G0832 Datasheet
Part 74AUP1G0832
Description Low Power 3-Input AND-OR Gate
Feature www.
DataSheet4U.
com 74AUP1G0832 Low-pow er 3-input AND-OR gate Rev.
01 — 8 No vember 2006 Product data sheet 1.
Gene ral description The 74AUP1G0832 is a hi gh-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs ma kes the circuit tolerant to slower inpu t rise and fall times across the entire VCC range from 0.
8 V to 3.
6 V.
This de vice ensures a very low static and dyna mic power consumption across the entire VCC range from 0.
8 V to 3.
6 V.
This de vice is fully specified for partial po wer-down applicati .
Manufacture NXP
Datasheet
Download 74AUP1G0832 Datasheet

74AUP1G0832

74AUP1G0832
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74AUP1G0832

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