DatasheetsPDF.com

ISPLSI5256VE Dataheets PDF



Part Number ISPLSI5256VE
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description In-System Programmable 3.3V SuperWIDE High Density PLD
Datasheet ISPLSI5256VE DatasheetISPLSI5256VE Datasheet (PDF)

www.DataSheet4U.com ispLSI 5256VE ® In-System Programmable 3.3V SuperWIDE™ High Density PLD Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 12000 PLD Gates / 256 Macrocells — Up to 144 I/O Pins — 256 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders,.

  ISPLSI5256VE   ISPLSI5256VE


Document
www.DataSheet4U.com ispLSI 5256VE ® In-System Programmable 3.3V SuperWIDE™ High Density PLD Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 12000 PLD Gates / 256 Macrocells — Up to 144 I/O Pins — 256 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 165 MHz Maximum Operating Frequency — tpd = 6.0 ns Propagation Delay — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels — Electrically Erasable and Reprogrammable — Non-Volatile — Programmable Speed/Power Logic Path Optimization • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE • ARCHITECTURE FEATURES — Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs — Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell — Macrocells Support Concurrent Combinatorial and Registered Functions — Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable — Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks — Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options — Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell Functional Block Diagram Input Bus Generic Logic Block Input Bus Generic Logic Block Boundary Scan Interface Generic Logic Block Generic Logic Block Input Bus Input Bus Global Routing Pool (GRP) Generic Logic Block Generic Logic Block Input Bus Input Bus Generic Logic Block Generic Logic Block Input Bus Input Bus ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com January 2002 5256ve_10 1 Specifications ispLSI 5256VE Functional Block Diagram Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option) I/O 143 I/O 142 I/O 141 I/O 140 I/O 129 I/O 128 I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 111 I/O 110 I/O 109 I/O 108 GOE0 GOE1 Input Bus Generic Logic Block Input Bus Generic Logic Block Boundary Scan Interface TMS TCK TDI TDO VCCIO 1TOE I/O 1 I/O 2 I/O 3 Generic Logic Block Input Bus I/O 107 I/O 106 I/O 105 I/O 104 Generic Logic Block Input Bus I/O 14 I/O 15 I/O 16 I/O 17 I/O 93 I/O 92 I/O 91 I/O 90 Generic Logic Block Input Bus I/O 18 I/O 19 I/O 20 I/O 21 Global Routing Pool (GRP) Generic Logic Block I/O 89 I/O 88 I/O 87 I/O 86 Input Bus I/O 32 I/O 33 I/O 34 I/O 35 I/O 75 I/O 74 I/O 73 I/O 72 Generic Logic Block Generic Logic Block Input Bus RESET Input Bus I/O 54 I/O 55 I/O 56 I/O 57 CLK 0 CLK 1 1CLK 2 1CLK 3 I/O 36 I/O 37 I/O 38 I/O 39 1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine which I/O is shared by package type. Package Type 100 TQFP 128 TQFP 256 fpBGA 272 BGA I/O 50 I/O 51 I/O 52 I/O 53 1/O 44 / CLK2 I/O 59 / CLK2 I/O 119 / CLK2 I/O 119 / CLK2 Multplexed Signals I/O 49 / CLK 3 I/O 65 / CLK3 I/O 131 / CLK3 I/O 131 / CLK3 I/O 68 I/O 69 I/O 70 I/O 71 I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE I/O 0 / .


IRKTF180 ISPLSI5256VE IXC


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)