ADSP-21367 SHARC Processor Datasheet

ADSP-21367 Datasheet, PDF, Equivalent


Part Number

ADSP-21367

Description

SHARC Processor

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADSP-21367 Datasheet


ADSP-21367
SHARC Processor
ADSP-21367/ADSP-21368/ADSP-21369
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
sample rate converter, precision clock generators, and
more. For complete ordering information, see Ordering
Guide on Page 61.
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter
4 independent asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in 256-ball BGA_ED and 208-lead LQFP_EP
packages
SIMD Core
Instruction
Cache
5 stage
Sequencer
DAG1/2
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
S
DMD 64-BIT
PMD
64-BIT
Core Bus
Cross Bar
PERIPHERAL BUS
32-BIT
PMD 64-BIT
EPD BUS 32-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
IOD1
32-BIT
PERIPHERAL BUS
IOD0 BUS
MTM
EP
CORE PCG
FLAGS C-D
TIMER
2-0
TWI
SPI/B
UART
1-0
S/PDIF PCG
Tx/Rx A-D
ASRC IDP/ SPORT
3-0 PDAP 7-0
7-0
CORE PWM
FLAGS 3-0
AMI SDRAM
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
External Port Pin MUX
Peripherals
External
Port
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

ADSP-21367
ADSP-21367/ADSP-21368/ADSP-21369
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 7
I/O Processor Features ......................................... 10
System Design .................................................... 10
Development Tools ............................................. 11
Additional Information ........................................ 12
Related Signal Chains .......................................... 12
Pin Function Descriptions ....................................... 13
Specifications ........................................................ 16
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 17
Package Information ........................................... 18
ESD Caution ...................................................... 18
Maximum Power Dissipation ................................. 18
Absolute Maximum Ratings ................................... 18
Timing Specifications ........................................... 18
Output Drive Currents ......................................... 51
Test Conditions .................................................. 51
Capacitive Loading .............................................. 51
Thermal Characteristics ........................................ 53
256-Ball BGA_ED Pinout ......................................... 54
208-Lead LQFP_EP Pinout ....................................... 57
Package Dimensions ............................................... 59
Surface-Mount Design .......................................... 60
Automotive Products .............................................. 61
Ordering Guide ..................................................... 61
REVISION HISTORY
10/13—Rev. E to Rev. F
Updated Development Tools ..................................... 11
Added Related Signal Chains ..................................... 12
Corrected EMU pin type from O/T(pu) to O(O/D, pu) in
Pin Function Descriptions ........................................ 13
Corrected Junction Temperature 256-Ball BGA Min Value at
ambient temperature (–40°C to +85C) from 0 to –40 in
Operating Conditions .............................................. 16
Added 400 MHz Min and Max values for Junction Temperature
208-Lead LQFP_EP at ambient temperature 0°C to +70C in
Operating Conditions .............................................. 16
Added footnote 2 to Table 24 in Memory Read .............. 30
Changed Max values in Table 34 in Pulse-Width Modulation
Generators ............................................................ 41
Updated timing parameters in Table 40 and in Figure 36 in
SPI Interface—Master .............................................. 48
Updated Figure 37 in SPI Interface—Slave .................... 49
Changes to Ordering Guide ....................................... 61
To view product/process change notifications (PCNs) related to
this data sheet revision, please visit the processor’s product page
on the www.analog.com website and use the View PCN link.
Rev. F | Page 2 of 64 | October 2013


Features SHARC Processor ADSP-21367/ADSP-21368/AD SP-21369 SUMMARY High performance 32-b it/40-bit floating-point processor opti mized for high performance audio proces sing Single-instruction, multiple-data (SIMD) computational architecture On-ch ip memory—2M bits of on-chip SRAM and 6M bits of on-chip mask programmable R OM Code compatible with all other membe rs of the SHARC family The ADSP-21367/A DSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with u nique audiocentric peripherals such as the digital applications interface, S/P DIF transceiver, serial ports, 8-channe l asynchronous sample rate converter, p recision clock generators, and more. Fo r complete ordering information, see Or dering Guide on Page 61. DEDICATED AUD IO COMPONENTS S/PDIF-compatible digital audio receiver/transmitter 4 independe nt asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based secur ity features include JTAG access to memory permitted with a 64-bi.
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