CY7C1442AV33

www.DataSheet4U.com PRELIMINARY CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Features Supports bus operation up to 250 MHz Available speed grades are 250, 200,167 MHz Registered inputs and outputs for pipelined operation 3.3V core power supply 2.5V/3.3V I/O operation Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 3.2 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) Provide high-performance 3-1-1-1 access rate User-selectable burst counter supporting Pentium® interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous output enable Single Cycle Chip Deselect Offered in JEDEC-standard 100-pin TQFP, 165-Ball fBGA and 209-Ball fBGA packages Also available in lead-free packages IEEE 1149.1 JTAG-Compatible Boundary Scan “ZZ” Sleep Mode Option Intel® Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and...