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CY7C1446AV33 Dataheets PDF



Part Number CY7C1446AV33
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C144xAV33) Sync SRAM
Datasheet CY7C1446AV33 DatasheetCY7C1446AV33 Datasheet (PDF)

www.DataSheet4U.com PRELIMINARY CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 3.2 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Provide high-performance 3-1-1-1 access rate • U.

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www.DataSheet4U.com PRELIMINARY CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200,167 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 3.2 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 165-Ball fBGA and 209-Ball fBGA packages • Also available in lead-free packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option Intel® Functional Description[1] The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM integrates 1,048,576 x 36, 2,097,152 x 18 and 524,288 x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 475 100 200 MHz 3.2 425 100 167 MHz 3.4 375 100 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3, CE2 are for TQFP and 165 fBGA package only. Cypress Semiconductor Corporation Document #: 38-05383 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 31, 2005 PRELIMINARY Logic Block Diagram – CY7C1440AV33 (1 Mbit x 36) A0, A1, A CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 ADSC ADSP BWD DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER BURST COUNTER CLR AND Q0 LOGIC DQD ,DQPD BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE DRIVER BWC MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E BWB DQs DQPA DQPB DQPC DQPD BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Logic Block Diagram – CY7C1442AV33 (2 Mbit x 18) A0, A1, A MODE ADDRESS REGISTER 2 A[1:0] ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER MEMORY ARRAY BWA BWE GW CE1 CE2 CE3 OE ENABLE REGISTER DQA,DQPA WRITE REGISTER DQA,DQPA WRITE DRIVER SENSE AMPS BWB OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Document #: 38-05383 Rev. *B Page 2 of 27 PRELIMINARY Logic Block Diagram – CY7C1446AV33 (512K x 72) A0, A1,A CY7C1440AV33 CY7C1442AV33 CY7C1446AV33 ADDRESS REGISTER A[1:0] MODE ADV CLK Q1 BINARY COUNTER CLR Q0 ADSC ADSP BWH DQH, DQPH WRITE DRIVER DQF, DQPF WRITE DRIVER DQF, DQPF WRITE DRIVER DQE, DQPE WRITE DRIVER DQD, DQPD WRITE DRIVER DQH, DQPH WRITE DRIVER DQG, DQPG WRITE DRIVER DQF, DQPF WRITE DRIVER DQ E, DQP BYTE “a”E WRITE DRIVER DQD, DQPD WRITE DRIVER DQC, DQPC WRITE DRIVER SENSE AMPS BWG BWF BWE MEMORY ARRAY BWD BWC DQC, DQPC WRITE DRIVER OUTPUT REGISTERS BWB DQB, DQPB WRITE DRIVER DQB, DQPB WRITE DRIVER DQA, DQPA WRITE DRIVER OUTPUT BUFFERS E BWA BWE GW CE1 CE2 CE3 OE DQA, DQPA WRITE DRIVER ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS DQs DQPA DQPB DQPC DQPD DQPE DQPF DQPG DQPH ZZ SLEEP CONTROL Document #: 38-05383 Rev. *B Page 3 of 27 PRELIMINARY .


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