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RoboClock CY7B9950
2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
Features
• • • • • • • • • • • • • • • 2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz Output-output skew < 100 ps Cycle-cycle jitter < 100 ps ± 2% max output duty cycle Selectable output drive strength Selectable positive or negative edge synchronization Eight LVTTL outputs driving 50Ω terminated lines LVCMOS/LVTTL over-voltage-tolerant reference input Phase adjustments in 625-/1250-ps steps up to +7.5 ns 2x, 4x multiply and (1/2)x, (1/4)x divide ratios Spread-Spectrum-compatible Industrial temp. range: –40°C to +85°C 32-pin TQFP package
Description
The CY7B9950 RoboClock is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high-performance computer and communication systems. The user can program the phase of the output banks through nF[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from ± 12 mA to ± 24 mA(3.3V).
Block Diagram
TEST PE/HD FS VDDQ1
Pin Configuration
VDD
REF
3F0
32
31
30
29
28
27
26
3F1
3
1F1:0
3
Phase Select
1Q0 1Q1
4F0 4F1 PE/HD VDDQ4 4Q1 4Q0 VSS
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
25 24 23 22 1F1 1F0 sOE# VDDQ1 1Q0 1Q1 VSS VSS 21 20 19 18 17 2Q0
FB
PLL
CY7B9950
3
2F1:0
3
Phase Select
2Q0 2Q1
VDDQ3
3Q1
VSS
FS
3
3F1:0
3
Phase Select and /K
3Q1 VDDQ3
3
4F1:0
3
Phase Select and /M
4Q0 4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation Document #: 38-07338 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
VSS
3Q0
VDD
3Q0
2Q1
FB
• 408-943-2600 Revised March 4, 2003
2F1
REF
2F0
3
3
3
TEST
RoboClock CY7B9950
Pin Description
Pin 29 13 27 Name
REF
I/O[1]
I
Type
LVTTL/LVCMOS Reference Clock Input.
Description Feedback Input. When MID or HIGH, Disables Phase-locked Loop (PLL) (except for conditions of note 3). REF goes to outputs of Bank 1 and Bank 2. REF goes to outputs of Bank 3 and Bank 4 through output dividers K and M. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock, respectively. When at MID level, the output drive strength is increased and the outputs synchronize with the positive edge of the reference clock (see Table 6). Select frequency and phase of the outputs (see Tables 1, 2, 3, 4, and 5).
FB TEST
I I
LVTTL Three-level
22
sOE#
I, PD
Two-level
4
PE/HD
I, PU
Three-level
24, 23, 26, 25, 1, 32, 3, 2 31 19, 20, 15, 16, 10, 11, 6, 7 21 12 5 14,30 8,9,17,18, 28
nF[1:0]
I
Three-level
FS nQ[1:0]
I O
Three-level LVTTL
Selects VCO operating frequency range (see Table 4). Four banks of two outputs (see Tables 1, 2, and 3).
VDDQ1[2] PWR VDDQ3[2] PWR VDDQ4[2] PWR VDD[2] VSS PWR PWR
Power Power Power Power Power
Power supply for Bank 1 and Bank 2 output buffers (see Table 7 for supply level constraints). Power supply for Bank 3 output buffers (see Table 7 for supply level constraints). Power supply for Bank 4 output buffers (see Table 7 for supply level constraints). Power supply for internal circuitry (see Table 7 for supply level constraints). Ground. The three-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY7B9950 PLL operating frequency range that corresponds to each FS level is given in Table 3. Table 3. Frequency Range Select FS L M H PLL Frequency Range 24 to 50 MHz 48 to 100 MHz 96 to 200 MHz
Device Configuration
The outputs of the CY7B9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 1 and Table 2, respectively. Table 1. Output Divider Settings — Bank 3 3F[1:0] LL HH Other[4] K .