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M366S1654ETS Dataheets PDF



Part Number M366S1654ETS
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description SDRAM Unbuffered Module
Datasheet M366S1654ETS DatasheetM366S1654ETS Datasheet (PDF)

www.DataSheet4U.com 128MB, 256MB, 512MB Unbuffered DIMM SDRAM SDRAM Unbuffered Module 168pin Unbuffered Module based on 256Mb E-die 62/72-bit Non ECC/ECC Revision 1.4 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (June, 2003) - First release Revision 1.1 (September, 2003) - Corrected Typo Revision 1.2 (February, 2004) - Corrected typo. Revision 1.3 (M.

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www.DataSheet4U.com 128MB, 256MB, 512MB Unbuffered DIMM SDRAM SDRAM Unbuffered Module 168pin Unbuffered Module based on 256Mb E-die 62/72-bit Non ECC/ECC Revision 1.4 May 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (June, 2003) - First release Revision 1.1 (September, 2003) - Corrected Typo Revision 1.2 (February, 2004) - Corrected typo. Revision 1.3 (March. 2004) - Modified DC Characteristics Notes. Revision 1.4 (May, 2004) - Added Note 5. sentense of tRDL parameter SDRAM Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM 168Pin Unbuffered DIMM based on 256Mb E-die (x8, x16) Ordering Information Part Number M366S1654ETS-C7A M366S3253ETS-C7A M366S3253ETU-C7A M374S3253ETS-C7A M374S3253ETU-C7A M366S6453ETS-C7A M366S6453ETU-C7A M374S6453ETS-C7A M374S6453ETU-C7A Density 128MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB Organization 16M x 64 32M x 64 32M x 64 32M x 72 32M x 72 64M x 64 64M x 64 64M x 72 64M x 72 Component Composition 16Mx16(K4S561632E) * 4EA 32Mx8(K4S560832E) * 8EA 32Mx8(K4S560832E) * 8EA 32Mx8(K4S560832E) * 9EA 32Mx8(K4S560832E) * 9EA 32Mx8(K4S560832E)*16EA 32Mx8(K4S560832E)*16EA 32Mx8(K4S560832E)*18EA 32Mx8(K4S560832E)*18EA 54-TSOP(II) Component Package SDRAM Height 1,000mil 1,375mil 1,125mil 1,375mil 1,125mil 1,375mil 1,125mil 1,375mil 1,125mil Operating Frequencies 7A @CL3 Maximum Clock Frequency CL-tRCD-tRP(clock) 133MHz(7.5ns) 3-3-3 @CL2 100MHz(10ns) 2-2-2 Feature Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • • • • • Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PIN CONFIGURATIONS (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 **CS0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD **CLK0 VSS DU **CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 **CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD **CLK1 A12 VSS **CKE0 **CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 SDRAM Back DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **CLK3 NC SA0 SA1 SA2 VDD Note : 1. * These pins are not used in this module. 2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD. 3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module. 4. ** About these pins, Refer to the Block Diagram of each. Pin Description Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 ~ 3 CKE0, CKE1 CS0 ~ CS3 RAS CAS WE Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable Function Address input (Multiplexed) VDD VSS VREF REGE SDA SCL SA0 ~ 2 DU NC Pin Name DQM0 ~ 7 DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Don′t use No connection Function * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.4 May 2004 128MB, 256MB, 512MB Unbuffered DIMM PIN CONFIGURATION DESCRIPTION Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. SDRAM Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) Selects .


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