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SHARC Processor ADSP-21367/ADSP-21368/ADSP-21369
SUMMARY
High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of on-chip mask programmable ROM
Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 61.
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter 4 independent asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based security features include
JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit
access under program control to sensitive code PLL has a wide variety of software and hardware multi-
plier/divider ratios Available in 256-ball BGA_ED and 208-lead LQFP_EP
packages
SIMD Core
Instruction Cache
5 stage Sequencer
DAG1/2
Timer
PEx PEy
FLAGx/IRQx/ TMREXP
JTAG
Block 0 RAM/ROM
Internal Memory
Block 1 RAM/ROM
Block 2 RAM
Block 3 RAM
DMD 64-BIT
S
DMD 64-BIT
PMD 64-BIT
Core Bus Cross Bar
PERIPHERAL BUS 32-BIT
PMD 64-BIT EPD BUS 32-BIT
B0D 64-BIT
B1D 64-BIT
B2D 64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D 64-BIT
IOD1 32-BIT
PERIPHERAL BUS
IOD0 BUS
MTM
EP
CORE PCG FLAGS C-D
TIMER 2-0
TWI
SPI/B
UART 1-0
S/PDIF PCG Tx/Rx A-D
ASRC IDP/ SPORT 3-0 PDAP 7-0 7-0
CORE PWM FLAGS 3-0
AMI SDRAM
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
External Port Pin MUX
Peripherals
External Port
Figure 1. Functional Block Diagram
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Rev. F
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ADSP-21367/ADSP-21368/ADSP-21369
TABLE OF CONTENTS
Summary ............................................................... 1 Dedicated Audio Components ................................. 1
General Description ................................................. 3 SHARC Family Core Architecture ............................ 4 Family Peripheral Architecture ................................ 7 I/O Processor Features ......................................... 10 System Design .................................................... 10 Development Tools ............................................. 11 Additional Information ........................................ 12 Related Signal Chains .......................................... 12
Pin Function Descriptions ....................................... 13 Specifications ........................................................ 16
Operating Conditions .......................................... 16 Electrical Characteristics ....................................... 17 Package Information ........................................... 18
ESD Caution ...................................................... 18 Maximum Power Dissipation ................................. 18 Absolute Maximum Ratings ................................... 18 Timing Specifications ........................................... 18 Output Drive Currents ......................................... 51 Test Conditions .................................................. 51 Capacitive Loading .............................................. 51 Thermal Characteristics ........................................ 53 256-Ball BGA_ED Pinout ......................................... 54 208-Lead LQFP_EP Pinout ....................................... 57 Package Dimensions ............................................... 59 Surface-Mount Design .......................................... 60 Automotive Products .............................................. 61 Ordering Guide ..................................................... 61
REVISION HISTORY
10/13—Rev. E to Rev. F
Updated Development Tools ..................................... 11
Added Related Signal Chains ..................................... 12
Corrected EMU pin type from O/T(pu) to O(O/D, pu) in Pin Function Descript.