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CY2DP3110 Dataheets PDF



Part Number CY2DP3110
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description Differential Clock/Data Fanout Buffer
Datasheet CY2DP3110 DatasheetCY2DP3110 Datasheet (PDF)

www.DataSheet4U.com FastEdge™ Series CY2DP3110 1 of 2:10 Differential Clock/Data Fanout Buffer Features • Ten ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs (CLKA) • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable • 50 ps output-to-output skew • 150 ps device-to-device skew • 400 ps propagation delay (typical) • 1.2 ps RMS period jitter (max.) • 1.5 GHz Operation (2.7 GHz maximum toggle frequency) • PECL and HSTL mode supply ran.

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