CY2PP3115

www.DataSheet4U.com PRELIMINARY FastEdge™ Series CY2PP3115 1:15 Differential Fanout Buffer Features Fifteen ECL/PECL differential outputs grouped in four banks Two ECL/PECLdifferential inputs Hot-swappable/-insertable 50-ps output-to-output skew < 200-ps device-to-device skew Less than 2-pS intrinsic jitter < 500-ps propagation delay (typical) Operation up to 1.5 GHz PECL mode supply range: VCC = 2.375V to 3.465V with VEE = 0V ECL mode supply range: VEE = –2.375V to –3.465V with VCC = 0V Industrial temperature range: 52-pin 1.4mm TQFP package Temperature compensation like 100K ECL –40°C to 85°C Description The CY2PP3115 is a low-skew, low propagation delay 1-to-15 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low-signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths which are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2PP3115 may function not only as a differential clock buffer but also as a signal level translator and fanout on ECL/PECL single-ended signal to 15 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to VCC via ...