CY2PP3210

www.DataSheet4U.com FastEdge™ Series CY2PP3210 Dual 1:5 Differential Clock/Data Fanout Buffer Features Dual sets of five ECL/PECL differential outputs Two ECL/PECL differential inputs Hot-swappable/-insertable 50 ps output-to-output skew 150 ps device-to-device skew 500 ps propagation delay (typical) 0.8 ps RMS period jitter (max.) 1.5 GHz Operation (2.2 GHz max. toggle frequency) PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V Industrial temperature range: –40°C to 85°C 32-pin 1.4-mm TQFP package Temperature compensation like 100K ECL Pin compatible with MC100ES6210 Functional Description The CY2PP3210 is a low-skew, low propagation delay dual 1-to-5 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are differential internally. The CY2PP3210 may function not only as a differential clock buffer but also as a signal-level translator and fanout distributing a single-ended signal. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a...