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82541ER Dataheets PDF



Part Number 82541ER
Manufacturers Intel Corporation
Logo Intel Corporation
Description Gigabit Ethernet Controller
Datasheet 82541ER Datasheet82541ER Datasheet (PDF)

www.DataSheet4U.com 82541ER Gigabit Ethernet Controller Networking Silicon Datasheet Product Features ■ ■ ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — 3.3 V (5 V tolerant PCI signaling) MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive bu.

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www.DataSheet4U.com 82541ER Gigabit Ethernet Controller Networking Silicon Datasheet Product Features ■ ■ ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — 3.3 V (5 V tolerant PCI signaling) MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers PHY Specific — Integrated for 10/100/1000 Mb/s operation — IEEE 802.3ab Auto-Negotiation support — IEEE 802.3ab PHY compliance and compatibility — State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation ■ ■ ■ ■ — Automatic polarity detection — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation — Advanced packed filtering — Jumbo frame support up to 16 KB — Intelligent Interrupt generation (multiple packets per interrupt) Manageabiltiy — Network Device Class Power Management Specification 1.1 — Compliance with PCI Power Management 1.1 and ACPI 2.0 — SNMP and RMON statistic counters — D0 and D3 power states Additional Device — Four programmable LED outputs — On-chip power control circuitry — BIOS LAN Disable pin — JTAG (IEEE 1149.1) Test Access Port built in silicon Lead-freea 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative Revision 4.1 September 2006 Revision History Date Aug 2003 Mar 2004 Oct 2004 Revision 2.0 3.0 3.1 Non-classified release. Updated Section 4, “Voltage, Temperature, and Timing Specifications,” for the C-0 stepping. • • Corrected EEMODE signal description. Updated signal names to match design guide and reference schematics. • Added lead free information. • Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information. Nov 2004 3.2 • Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Package Information”. • Corrected pinout discrepancies between sections “Signal Descriptions” and “Package and Pinout Information”. • Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See Table 2, Recommended Operating Conditions and Table 6, DC Characteristics. • Updated Visual Pin Assignment diagram for pinouts F9, F10, E14, F14, and H14. • Removed all references to CLK_RUN# signal. Apr 2005 July 2005 Aug 2005 June 2006 June 2006 Aug 2006 Sept 2006 3.5 3.6 3.7 3.8 3.9 4.0 4.1 • Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an external pull-down resistor is required. • Added pin C8 description to Table 29 and Table 31. • Corrected 25 MHz Clock Input Requirements in Table 13. • Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is not used then an external pull-up resistor is required. • Updated Table 13 “25 MHz Clock Input Requirements”. • Updated Table 40 descriptions for pins A10, B10, and C9. • Updated pinout descriptions from Tables 25 - 42 to match Figure 13. • Removed note “b” from Table 2 and note “a” from Tables 3 and 4. Moved the note following Table 5 before Table 3 “3.3V Supply Voltage Ramp”. Notes Jan 2005 3.3 Feb 2005 3.4 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel.


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