HDMP-0482

www.DataSheet4U.com Agilent HDMP-0482 Octal Cell Port Bypass Circuit with CDR and Data Valid Detection Data Sheet Features Supports 1.0625 GBd fibre channel operation Supports 1.25 GBd Gigabit Ethernet (GE) operation Octal cell PBC/CDR in one package CDR location determined by choice of cable input/output Amplitude valid detection on FM_NODE[7] input Data valid detection on FM_NODE[0] input – Run length violation detection – Comma detection – Configurable for both singleframe and multi-frame detection Equalizers on all inputs High speed LVPECL I/O Buffered Line Logic (BLL) outputs (no external bias resistors required) 1.09 W typical power at Vcc=3.3V 64 Pin, 14 mm, low cost plastic QFP package Applications RAID, JBOD, BTS cabinets Four 2:1 muxes Four 1:2 buffers 1 = > N gigabit serial buffer N = > 1 gigabit serial mux Description The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: “di...