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HDMP-0482 Dataheets PDF



Part Number HDMP-0482
Manufacturers Hewlett-Packard
Logo Hewlett-Packard
Description Octal Cell Port Bypass Circuit
Datasheet HDMP-0482 DatasheetHDMP-0482 Datasheet (PDF)

www.DataSheet4U.com Agilent HDMP-0482 Octal Cell Port Bypass Circuit with CDR and Data Valid Detection Data Sheet Features • Supports 1.0625 GBd fibre channel operation • Supports 1.25 GBd Gigabit Ethernet (GE) operation • Octal cell PBC/CDR in one package • CDR location determined by choice of cable input/output • Amplitude valid detection on FM_NODE[7] input • Data valid detection on FM_NODE[0] input – Run length violation detection – Comma detection – Configurable for both singleframe and mu.

  HDMP-0482   HDMP-0482


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www.DataSheet4U.com Agilent HDMP-0482 Octal Cell Port Bypass Circuit with CDR and Data Valid Detection Data Sheet Features • Supports 1.0625 GBd fibre channel operation • Supports 1.25 GBd Gigabit Ethernet (GE) operation • Octal cell PBC/CDR in one package • CDR location determined by choice of cable input/output • Amplitude valid detection on FM_NODE[7] input • Data valid detection on FM_NODE[0] input – Run length violation detection – Comma detection – Configurable for both singleframe and multi-frame detection • Equalizers on all inputs • High speed LVPECL I/O • Buffered Line Logic (BLL) outputs (no external bias resistors required) • 1.09 W typical power at Vcc=3.3V • 64 Pin, 14 mm, low cost plastic QFP package Applications • RAID, JBOD, BTS cabinets • Four 2:1 muxes • Four 1:2 buffers • 1 = > N gigabit serial buffer • N = > 1 gigabit serial mux Description The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: “disk in loop” and “disk bypassed”. When the “disk in loop” mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0482’s TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC’s (e.g. an HDMP-1636A) Rx± differential input pins. Data from the Disk Drive Transceiver IC’s Tx± differential outputs goes to the HDMP-0482’s FM_NODE[n]± differential input pins. When the “disk bypassed” mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk. The “disk bypassed” mode is enabled by pulling the BYPASS[n]pin low. Leave BYPASS[n]floating to enable the “disk in loop” mode. HDMP-0482’s may be cascaded with other members of the HDMP-04XX/HDMP-05XX family through the FM_NODE and TO_NODE pins to accommodate any number of hard disks. The unused cells in this PBC may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0482 may also be used as eight 1:1 buffers, one with a CDR and seven without. For example, an HDMP-0482 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (nonCDR path). In addition, the HDMP-0482 may be configured as four 2:1 multiplexers or as four 1:2 buffers. HDMP-0482 CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). The HDMP-0482 design allows for CDR placement at any location with respect to the hard disk slots. For example, if the BYPASS[0]- pin is floating and hard disk slots A to G are connected to PBC cells 1 to 7, respectively, the CDR function will be performed before entering the hard disk at slot A. To obtain a CDR function after slot G, BYPASS[1]- must be floating and hard disk slots A to G must be connected to PBC cells 2,3,4,5,6,7 and 0, respectively. Table 1 shows all possible connections. For configurations where the CDR is before slot A, a Data Valid (FM_NODE[0]_DV) pin indicates whether the incoming data on FM_NODE[0]± is valid Fibre Channel data. In addition, an Amplitude Valid (FM_NODE[7]AV) pin shows the status of the signal at FM_NODE[7]. 7 0 FM_NODE(7)_AV AV 1 BYPASS1 2 BYPASS2 3 BYPASS3 4 BYPASS4 5 BYPASS5 6 BYPASS6 1 0 1 0 1 0 1 0 1 0 1 0 1 0 BYPASS7 1 0 0 1 FM_NODE[0]_DV DV CDR MODE_VDD BYPASS0 FSEL REFCLK RFCM MODE_VDD BYPASS0 Figure 1. Block Diagram of HDMP-0482. HDMP-0482 Block Diagram CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external training controls. It does this by continually frequency locking onto the 106.25 MHz reference clock (REFCLK) and then phase locking onto the input data stream. Once bit locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded. DV Output The Data Valid (DV) block detects if the incoming data on FM_NODE[0]± is valid Fibre Channel data. The DV checks for sufficient K28.5+ characters (per Fibre Channel framing rules) and for run len.


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