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HDMP-0552 Dataheets PDF



Part Number HDMP-0552
Manufacturers Hewlett-Packard
Logo Hewlett-Packard
Description QUAD PORT BYPASS CIRCUIT
Datasheet HDMP-0552 DatasheetHDMP-0552 Datasheet (PDF)

www.DataSheet4U.com Agilent HDMP-0552 Quad Port Bypass Circuit with CDR and Data Valid Detection For Fibre Channel Arbitrated Loops Data Sheet Features • Supports 1.0625/2.125 GBd Fibre Channel operation • Quad PBC/CDR in one package • CDR location determined by choice of cable input/output • Amplitude valid detection on FM_NODE[0] input • Data valid detection on FM_NODE[0] input – Run length violation detection – Comma detection – Configurable for both singleframe and multi-frame detection • .

  HDMP-0552   HDMP-0552


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www.DataSheet4U.com Agilent HDMP-0552 Quad Port Bypass Circuit with CDR and Data Valid Detection For Fibre Channel Arbitrated Loops Data Sheet Features • Supports 1.0625/2.125 GBd Fibre Channel operation • Quad PBC/CDR in one package • CDR location determined by choice of cable input/output • Amplitude valid detection on FM_NODE[0] input • Data valid detection on FM_NODE[0] input – Run length violation detection – Comma detection – Configurable for both singleframe and multi-frame detection • Speed select pin for 1 or 2 GBd operation • Single REFCLK for 1 or 2 GBd operation • CDR selectable via external pin • Enable/disable equalizers on all inputs • Enable/disable selected highspeed output drivers • High speed LVPECL I/O • Buffered line logic (BLL) outputs (no external bias resistors required) • 1.1 W typical power at VCC = 3.3 V • Advanced 0.35 µ BiCMOS technology • 64 Pin, 10 mm, low cost plastic QFP package Applications • RAID, JBOD, BTS cabinets • 1=> 1-4 serial buffer with or without CDR Description The HDMP-0552 is a Quad Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. See Figure 1 for block diagram. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: “disk in loop” and “disk bypassed.” When the “disk in loop” mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0552’s TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC (for example, an HDMP-263x) Rx± differential input pins. Data from the Disk Drive Transceiver IC Tx± differential output pins goes to HDMP-0552’s FM_NODE[n]± differential input pins. Figure 2 and Figure 3 show connection diagrams for disk drive array applications. When the “disk bypassed” mode is selected, the disk drive is either absent or nonfunctional, and the loop bypasses the hard disk. Multiple HDMP-0552’s may be cascaded or connected to other members of the HDMP-04xx family through the FM_LOOP and TO_LOOP pins to create loops for arrays of disk drives greater than 4. See Table 3 to identify which of the 5 cells (0:4) provides FM_LOOP, TO_LOOP pins (cell connected to cable). CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). Combinations of Quad PBCs can be utilized to accommodate any number of hard disks. The unused cells in a quad may be bypassed with pulldown resistors on the BYPASS[n]- pins for these cells. Additional power savings possible by turning off unused output drives. Please refer to BLL output section on page 3. An HDMP-0552 can be wired as a single or double mux cell with a CDR. It may also be used as a single or double mux cell without a CDR. All TO_NODE outputs of the HDMP-0552 are of equal strength. Therefore, this part may be used as a 1=>1- 4 buffer. The design of HDMP-0552 allows for placement of the CDR at any location with respect to hard disk slots. For example, if BYPASS[0]pin is tied to VCC and hard disk slots A to D are connected to PBC cells 1 to 4 in the same order, the CDR function is performed at entry to the HDMP-0552 (Figure 2). To achieve a CDR function at exit from the HDMP-0552, BYPASS[1]- must be tied to VCC and hard disk slots A to D must be connected to PBC cells 2, 3, 4, 0 in that order (Figure 3). Table 3 shows all possible connections. In case of CDR at entry, a Signal Detect (SD) pin shows the status of the signal at the incoming cable. The recommended method of setting the BYPASS[i]- pins HIGH is to drive them with a high-impedance signal. Internal pull-up resistors force the BYPASS[i]- pins to VCC. HDMP-0552 Block Diagram CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external training controls. It does this by 2 continually frequency locking onto the reference clock (REFCLK) and then phase locking onto the input data stream. Once bit-locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded. Data Valid Output The outgoing data from the CDR is checked for two types of errors. First, the data is checked for “.


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