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DS26524 Quad T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26524 is a single-chip 4-port framer and line interface unit (LIU) combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul lines.
FEATURES
Four Complete T1, E1, or J1 Long-Haul/ShortHaul Transceivers (LIU plus Framer) Independent T1, E1, or J1 Selections for Each Transceiver Internal Software-Selectable Transmit- and Receive-Side Termination for 100Ω T1 Twisted Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair, and 75Ω E1 Coaxial Applications Crystal-Less Jitter Attenuator can be Selected for Transmit or Receive Path; Jitter Attenuator Meets ETS CTR 12/13, ITU-T G.736, G.742, G.823, and AT&T Pub 62411 External Master Clock can be Multiple of 2.048MHz or 1.544MHz for T1/J1 or E1 Operation; This Clock is Internally Adapted for T1 or E1 Usage in the Host Mode Receive-Signal Level Indication from -2.5dB to -36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments Transmit Open- and Short-Circuit Detection LIU LOS in Accordance with G.775, ETS 300 233, and T1.231
APPLICATIONS
Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment
TYPICAL OPERATING CIRCUIT
DS26524
T1/E1/J1 NETWORK
T1/J1/E1 Transceiver
x4
BACKPLANE
Transmit Synchronizer Flexible Signaling Extraction and Insertion Using Either the System Interface or Microprocessor Port Alarm Detection and Insertion T1 Framing Formats of D4, SLC-96, and ESF
TDM
ORDERING INFORMATION
PART DS26524GN DS26524GN+ TEMP RANGE -40°C to +85°C -40°C to +85°C PIN-PACKAGE 256 TE-CSBGA 256 TE-CSBGA
J1 Support E1 G.704 and CRC-4 Multiframe T1-to-E1 Conversion Features Continued in Section 2.
+ Denotes lead-free/RoHS compliant device.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 102106
DS26524 Quad T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
1.1
DETAILED DESCRIPTION.................................................................................................9
MAJOR OPERATING MODES .............................................................................................................9
2.
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
FEATURE HIGHLIGHTS ..................................................................................................10
GENERAL ......................................................................................................................................10 LINE INTERFACE ............................................................................................................................10 CLOCK SYNTHESIZER ....................................................................................................................10 JITTER ATTENUATOR .....................................................................................................................10 FRAMER/FORMATTER ....................................................................................................................10 SYSTEM INTERFACE ......................................................................................................................11 HDLC CONTROLLERS ...................................................................................................................12 TEST AND DIAGNOSTICS ................................................................................................................12 MICROCONTROLLER PARALLEL PORT.............................................................................................12
3. 4. 5. 6. 7.
7.1
APPLICATIONS ...............................................................................................................13 SPECIFICATIONS COMPLIANCE ...................................................................................14 ACRONYMS AND GLOSSARY .......................................................................................16 BLOCK DIAGRAMS.........................................................................................................17 PIN DESCRIPTIONS ........................................................................................................19
PIN FUNCTIONAL DESCRIPTION ......................................................................................................19
8.
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8
FUNCTIONAL DESCRIPTION .........................................................................................26
MICROPROCESSOR INTERFACE ......................................................................................................26
Parallel Port Mode........................................................................................