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VSC7216-01 Dataheets PDF



Part Number VSC7216-01
Manufacturers Vitesse Semiconductor
Logo Vitesse Semiconductor
Description Multi-Gigabit Interconnect
Datasheet VSC7216-01 DatasheetVSC7216-01 Datasheet (PDF)

www.DataSheet4U.com VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7216-01 Features • 4 ANSI X3T11 Fibre Channel and IEEE 802.3z Gigabit Ethernet Compliant Transceivers • Over 8 Gb/s Duplex Raw Data Rate • Redundant PECL Tx Outputs and Rx Inputs • 8B/10B Encoder/Decoder per Channel, Optional Encoder/Decoder Bypass Operation • “ASIC-FriendlyTM” Timing Options for Transmitter Parallel Input Data • Elastic Buffers for Intra/Inter-Chip Cable Deskewing and Channel-to-Channel Alignment .

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www.DataSheet4U.com VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC7216-01 Features • 4 ANSI X3T11 Fibre Channel and IEEE 802.3z Gigabit Ethernet Compliant Transceivers • Over 8 Gb/s Duplex Raw Data Rate • Redundant PECL Tx Outputs and Rx Inputs • 8B/10B Encoder/Decoder per Channel, Optional Encoder/Decoder Bypass Operation • “ASIC-FriendlyTM” Timing Options for Transmitter Parallel Input Data • Elastic Buffers for Intra/Inter-Chip Cable Deskewing and Channel-to-Channel Alignment • Tx/Rx Rate Matching via IDLE Insertion/Deletion • Compatible with VSC7211/7212/7214 Multi-Gigabit Interconnect Chip • Received Data Aligned to Local REFCLK or to Recovered Clock • PECL Rx Signal Detect and Cable Equalization • Per-Channel Serial Tx-to-Rx and Parallel Rxto-Tx Internal Loopback Modes • Clock Multiplier Generates Baud Rate Clock • Automatic Lock-to-Reference • JTAG Boundary Scan Support for TTL I/O • Built-In Self Test • 3.3V Supply, 3.0W • 256-Pin, 27mm BGA package VSC7216-01 Block Diagram TRANSMITTER PTXEND TD(7:0) C/DD WSEND RECEIVER LBTXD PTXD+ PTXDRTXD+ RTXDLBEND(1:0) RXP/RD PRXD+ PRXDRRXD+ RRXDLBENC(1:0) RXP/RC PRXC+ PRXCRRXC+ RRXCLBENB(1:0) RXP/RB PRXB+ PRXBRRXB+ RRXBLBENA(1:0) RXP/RA PRXA+ PRXARRXA+ RRXA- 8 D Q 8 8B/10B 10 Encode RTXEND PTXENC Clk/Data Recovery PSDETD RSDETD 10 8B/10B Decode 8 3 8 Elastic Buffer RD(7:0) IDLED KCHD ERRD RCLKD RCLKDN TC(7:0) C/DC WSENC 8 D Q 8 LBTXC PTXC+ PTXCRTXC+ RTXC- 8B/10B 10 Encode RTXENC PTXENB Clk/Data Recovery PSDETC RSDETC 10 8B/10B Decode 8 3 8 Elastic Buffer RC7:0) IDLEC KCHC ERRC RCLKC RCLKCN TB(7:0) C/DB WSENB 8 D Q 8 LBTXB PTXB+ PTXBRTXB+ RTXB- 8B/10B 10 Encode RTXENB PTXENA Clk/Data Recovery PSDETB RSDETB 10 8B/10B Decode 8 3 8 Elastic Buffer RB(7:0) IDLEB KCHB ERRB RCLKB RCLKBN TA(7:0) C/DA WSENA KCHAR 8 D Q 8 LBTXA PTXA+ PTXARTXA+ RTXA- 8B/10B 10 Encode 4 RTXENA Clk/Data Recovery PSDETA RSDETA 10 8B/10B Decode 8 3 8 Elastic Buffer RA(7:0) IDLEA KCHA ERRD RCLKA RCLKAN WSI FLOCK Channel Align WSO TBCA TBCB TBCC TBCD DUAL REFCLKP REFCLKN Tx Clock x20/x10 Clock Gen CAP0 CAP1 REFCLK TBERRA TBERRB TBERRC TBERRD TMODE(2:0) RMODE(1:0) RESETN ENDEC BIST TRSTN TMS TDI TCK JTAG Boundary Scan TDO G52352-0, Rev 3.2 05/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION Multi-Gigabit Interconnect Chip Multi-Gigabit Interconnect Chip Preliminary Data Sheet VSC7216-01 VSC7216 General Description The VSC7216-01 is a quad, 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high bandwidth interconnection between busses, backplanes, or other subsystems. Four Fibre Channel and Gigabit Ethernet compliant transceivers provide up to 8.32Gb/s of duplex raw data transfer. Each channel can be operated at a maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 392Mb/s (8 bits at 49MHz). For the entire chip in duplex mode, the aggregate transfer rate is between 6.3Gb/s and 8.7Gb/s. The VSC7216-01 contains four 8B/10B encoders, serializers, de-serializers, 8B/10B decoders and elastic buffers which provide the user with a simple interface for transferring data serially and recovering it on the receive side. The device can also be configured to operate as four non-encoded 10-bit transceivers. Notation In this document, each of the four channels are identified as channel A, B, C or D. When discussing a signal on any specific channel, the signal will have the channel letter embedded in the name, e.g., TA(7:0). When referring to the common behavior of a signal which is used on each of the four channels, a lower case “n” is used in the signal name, e.g., Tn(7:0). Differential signals (e.g., PTXA+ and PTXA-) may be referred to as a single signal, i.e. PTXA, by dropping reference to the “+” and “-”. REFCLK refers either to the PECL/TTL input pair REFCLKP/REFCLKN, which can be differential PECL (using both REFCLKP and REFCLKN) or single-ended TTL (using REFCLKP and leaving REFCLKN open). Clock Synthesizer Depending on the state of the DUAL input, the VSC7216-01 clock synthesizer multiplies the reference frequency provided on the REFCLK input by 10 (DUAL is LOW) or 20 (DUAL is HIGH) to achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient (NPO is preferred but X7R may be acceptable). These capacitors are used to minimize the impact of common-mode noise on the Clock Multiplier Unit, especially power supply noise. Higher value capacitors provide better robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply nois.


TTR-1A23 VSC7216-01 XE0002B


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