HLX6228 SOI Datasheet

HLX6228 Datasheet, PDF, Equivalent


Part Number

HLX6228

Description

128K x 8 STATIC RAM-Low Power SOI

Manufacture

Honeywell

Total Page 12 Pages
Datasheet
Download HLX6228 Datasheet


HLX6228
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Military & Space Products
128K x 8 STATIC RAM—Low Power SOI
HLX6228
FEATURES
RADIATION
• Fabricated with RICMOSIV Silicon on Insulator
(SOI) 0.7 µm Low Power Process (Leff = 0.55 µm)
• Total Dose Hardness through 1x106 rad(Si)
• Neutron Hardness through 1x1014 cm-2
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• Dose Rate Survivability through 1x1011 rad(Si)/s
• Soft Error Rate of <1x10-10 Upsets/bit-day in Geosyn-
chronous Orbit
• No Latchup
OTHER
• Read/Write Cycle Times
32 ns (-55 to 125°C)
• Typical Operating Power <9 mW/MHz
• JEDEC Standard Low Voltage
CMOS Compatible I/O
• Single 3.3 V ± 0.3 V Power Supply
• Asynchronous Operation
• Packaging Options
– 32-Lead CFP (0.820 in. x 0.600 in.)
– 40-Lead CFP (0.775 in. x 0.710 in.)
GENERAL DESCRIPTION
The 128K x 8 Radiation Hardened Static RAM is a high
performance 131,072 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell’s radiation hardened technology, and is
designed for use in low voltage systems operating in radiation
environments. The RAM operates over the full military
temperature range and requires only a single 3.3 V ± 0.3V
power supply. The RAM is compatible with JEDEC standard
low voltage CMOS I/O. Power consumption is typically less
than 9 mW/MHz in operation, and less than 2 mW when de-
selected. The RAM read operation is fully asynchronous, with
an associated typical access time of 32 ns at 3.3 V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensi-
tive CMOS) technology is radiation hardened through the use
of advanced and proprietary design, layout and process
hardening techniques.TheRICMOS™IVlow power process is
a SIMOX CMOS technology with a 150 Å gate oxide and a
minimum drawn feature size of 0.7 µm (0.55 µm effective gate
length—L ). Additional features include tungsten via plugs,
eff
Honeywell’s proprietary SHARP planarization process and a
lightly doped drain (LDD) structure for improved short channel
reliability. A 7 transistor (7T) memory cell is used for superior
single event upset hardening, while three layer metal power
bussing and the low collection volume SIMOX substrate
provide improved dose rate hardening.
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.myspaceparts.com

HLX6228
HLX6228
FUNCTIONAL DIAGRAM
A:3-7,12,14-16
CE
NCS
NWE
NOE
9
A:0-2, 8-11, 13
8
Row
Decoder
131,072 x 8
Memory
Array
•••
Column Decoder
Data Input/Output
WE • CS • CE
8
8
DQ:0-7
NWE • CS • CE • OE
(0 = high Z)
1 = enabled
Signal
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-16 Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. This part must be Read and Write controlled using the NCS pin: it
requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse
to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched.
The part must be controlled in this fashion to meet the timing specifications defined.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE NWE NOE
MODE
DQ
L H H L Read Data Out
L
H
LX
Write
Data In
Notes:
X: VI=VIH or VIL
H X XX XX Deselected High Z
XX: VSSVIVDD
X L XX XX Disabled High Z NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
2


Features www.DataSheet4U.com Military & Space Pr oducts HLX6228 128K x 8 STATIC RAM— Low Power SOI FEATURES RADIATION • Fa bricated with RICMOS™ IV Silicon on I nsulator (SOI) 0.7 µm Low Power Proces s (Leff = 0.55 µm) • Total Dose Hard ness through 1x106 rad(Si) • Neutron Hardness through 1x1014 cm-2 • Dynami c and Static Transient Upset Hardness t hrough 1x109 rad(Si)/s • Dose Rate Su rvivability through 1x1011 rad(Si)/s Soft Error Rate of <1x10-10 Upsets/bi t-day in Geosynchronous Orbit • No La tchup OTHER • Read/Write Cycle Times ≤ 32 ns (-55 to 125°C) • Typical O perating Power <9 mW/MHz • JEDEC Stan dard Low Voltage CMOS Compatible I/O Single 3.3 V ± 0.3 V Power Supply Asynchronous Operation • Packaging Options – 32-Lead CFP (0.820 in. x 0. 600 in.) – 40-Lead CFP (0.775 in. x 0 .710 in.) GENERAL DESCRIPTION The 128K x 8 Radiation Hardened Static RAM is a high performance 131,072 word x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell’s rad.
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