Power SOI. HLX6228 Datasheet

HLX6228 SOI. Datasheet pdf. Equivalent


Honeywell HLX6228
www.DataSheet4U.com
Military & Space Products
128K x 8 STATIC RAM—Low Power SOI
HLX6228
FEATURES
RADIATION
• Fabricated with RICMOSIV Silicon on Insulator
(SOI) 0.7 µm Low Power Process (Leff = 0.55 µm)
• Total Dose Hardness through 1x106 rad(Si)
• Neutron Hardness through 1x1014 cm-2
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• Dose Rate Survivability through 1x1011 rad(Si)/s
• Soft Error Rate of <1x10-10 Upsets/bit-day in Geosyn-
chronous Orbit
• No Latchup
OTHER
• Read/Write Cycle Times
32 ns (-55 to 125°C)
• Typical Operating Power <9 mW/MHz
• JEDEC Standard Low Voltage
CMOS Compatible I/O
• Single 3.3 V ± 0.3 V Power Supply
• Asynchronous Operation
• Packaging Options
– 32-Lead CFP (0.820 in. x 0.600 in.)
– 40-Lead CFP (0.775 in. x 0.710 in.)
GENERAL DESCRIPTION
The 128K x 8 Radiation Hardened Static RAM is a high
performance 131,072 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated
with Honeywell’s radiation hardened technology, and is
designed for use in low voltage systems operating in radiation
environments. The RAM operates over the full military
temperature range and requires only a single 3.3 V ± 0.3V
power supply. The RAM is compatible with JEDEC standard
low voltage CMOS I/O. Power consumption is typically less
than 9 mW/MHz in operation, and less than 2 mW when de-
selected. The RAM read operation is fully asynchronous, with
an associated typical access time of 32 ns at 3.3 V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensi-
tive CMOS) technology is radiation hardened through the use
of advanced and proprietary design, layout and process
hardening techniques.TheRICMOS™IVlow power process is
a SIMOX CMOS technology with a 150 Å gate oxide and a
minimum drawn feature size of 0.7 µm (0.55 µm effective gate
length—L ). Additional features include tungsten via plugs,
eff
Honeywell’s proprietary SHARP planarization process and a
lightly doped drain (LDD) structure for improved short channel
reliability. A 7 transistor (7T) memory cell is used for superior
single event upset hardening, while three layer metal power
bussing and the low collection volume SIMOX substrate
provide improved dose rate hardening.
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.myspaceparts.com


HLX6228 Datasheet
Recommendation HLX6228 Datasheet
Part HLX6228
Description 128K x 8 STATIC RAM-Low Power SOI
Feature HLX6228; www.DataSheet4U.com Military & Space Products HLX6228 128K x 8 STATIC RAM—Low Power SOI FEATURES .
Manufacture Honeywell
Datasheet
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Honeywell HLX6228
HLX6228
FUNCTIONAL DIAGRAM
A:3-7,12,14-16
CE
NCS
NWE
NOE
9
A:0-2, 8-11, 13
8
Row
Decoder
131,072 x 8
Memory
Array
•••
Column Decoder
Data Input/Output
WE • CS • CE
8
8
DQ:0-7
NWE • CS • CE • OE
(0 = high Z)
1 = enabled
Signal
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-16 Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. This part must be Read and Write controlled using the NCS pin: it
requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse
to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched.
The part must be controlled in this fashion to meet the timing specifications defined.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE NWE NOE
MODE
DQ
L H H L Read Data Out
L
H
LX
Write
Data In
Notes:
X: VI=VIH or VIL
H X XX XX Deselected High Z
XX: VSSVIVDD
X L XX XX Disabled High Z NOE=H: High Z output state maintained
for NCS=X, CE=X, NWE=X
2



Honeywell HLX6228
HLX6228
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electri-
cal and timing performance parameters will remain within
specifications after rebound at VDD = 3.6 V and T =125°C
extrapolated to ten years of operation. Total dose hard-
ness is assured by wafer level testing of process monitor
transistors and RAM product using 10 KeV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 KeV X-rays applied at
a dose rate of 1x105 rad(Si)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must accommo-
date these effects.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under rec-
ommended operating conditions. To ensure validity of all
specified performance parameters before, during, and
after radiation (timing degradation during transient pulse
radiation (timing degradation during transient pulse ra-
diation is 10%), it is suggested that stiffening capaci-
tance be placed on or near the package VDD and VSS,
with a maximum inductance between the package (chip)
and stiffening capacitance of 0.7 nH per part. If there are
no operate-through or valid stored data requirements,
typical circuit board mounted de-coupling capacitors are
recommended.
Soft Error Rate
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under recom-
mended operating conditions. Fabrication with the
SIMOX substrate material provides oxide isolation be-
tween adjacent PMOS and NMOS transistors and elimi-
nates any potential SCR latchup structures. Sufficient
transistor body tie connections to the p- and n-channel
substrates are made to ensure no source/drain snapback
occurs.
RADIATION HARDNESS RATINGS (1)
Parameter
Limits (2)
Units
Total Dose
1x106
rad(Si)
Transient Dose Rate Upset
1x109
rad(Si)/s
Transient Dose Rate Survivability
1x1011
rad(Si)/s
Soft Error Rate
<1x10-10
upsets/bit-day
Neutron Fluence
1x1014
N/cm2
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.
3
Test Conditions
TA=25°C
Pulse width 1 µs
Pulse width 50 ns, X-ray,
VDD=4.0 V, TA=25°C
TA=125°C, Adams 90%
worst case environment
1 MeV equivalent energy,
Unbiased, TA=25°C







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