DatasheetsPDF.com

HMN5128DV Dataheets PDF



Part Number HMN5128DV
Manufacturers Hanbit Electronics
Logo Hanbit Electronics
Description Non-Volatile SRAM MODULE 4Mbit
Datasheet HMN5128DV DatasheetHMN5128DV Datasheet (PDF)

www.DataSheet4U.com HANBit HMN5128DV Non-Volatile SRAM MODULE 4Mbit (512K x 8-Bit),32Pin-DIP, 3.3V Part No. HMN5128DV GENERAL DESCRIPTION The HMN5128DV Nonvolatile SRAM is a 4,194,304-bit static RAM organized as 524,288 bytes by 8 bits. The HMN5128DV has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. .

  HMN5128DV   HMN5128DV


Document
www.DataSheet4U.com HANBit HMN5128DV Non-Volatile SRAM MODULE 4Mbit (512K x 8-Bit),32Pin-DIP, 3.3V Part No. HMN5128DV GENERAL DESCRIPTION The HMN5128DV Nonvolatile SRAM is a 4,194,304-bit static RAM organized as 524,288 bytes by 8 bits. The HMN5128DV has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The HMN5128DV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-volatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES w Access time : 70, 85, 120, 150ns w High-density design : 4Mbit Design w Battery internally isolated until power is applied w Industry-standard 32-pin 512K x 8 pinout w Unlimited write cycles w Data retention in the absence of VCC w 10-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss w Conventional SRAM operation; unlimited write cycles PIN ASSIGNMENT A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 OPTIONS w Timing 70 ns 85 ns 120 ns 150 ns MARKING -70 -85 -120 -150 32-pin Encapsulated Package URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 1 HANBit Electronics Co.,Ltd. HANBit FUNCTIONAL DESCRIPTION HMN5128DV The HMN5128DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A0-A18) defines which of the 524,288 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable. When power is valid, the HMN5128DV operates as a standard CMOS SRAM. During power-down and power-up cycles, the HMN5128DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN5128DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge. The HMN5128DV provides full functional capability for Vcc greater than 3.0 V and write protects by 2.8 V nominal. Powerdown/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold VPFD. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “ don’t care” and all outputs are high impedance. As Vcc falls below approximately 2.5 V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.5 volts, the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 3.0 volts. BLOCK DIAGRAM PIN DESCRIPTION /OE /WE 512K x 8 SRAM Block Power A0-A18 A0-A18 : Address Input /CE : Chip Enable DQ0-DQ7 /CE CON VCC Vss : Ground DQ0-DQ7 : Data In / Data Out /WE : Write Enable /OE : Output Enable /CE Power – Fail Control Lithium Cell NC Connection VCC: :No Power (+3.3V) URL:www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002) 2 HANBit Electronics Co.,Ltd. HANBit TRUTH TABLE MODE Not selected Output disable Read Write /OE X H L X /CE H L L L /WE X H H L I/O OPERATION High Z High Z DOUT DIN HMN5128DV POWER Standby Active Active Active ABSOLUTE MAXIMUM RATINGS PARAMETER DC voltage applied on VCC relative to VSS DC Voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature Soldering temperature SYMBOL VCC VT TOPR TSTG TSOLDER RATING -0.5V to Vcc+0.5 -0.3V to 4.6V 0 to 70°C -65°C to 150°C 260°C For 10 second VT≤ VCC+0.3 CONDITIONS NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceed.


HMN5128D HMN5128DV HMN5128JV


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)