AS4LC4M4883C MODE Datasheet

AS4LC4M4883C Datasheet, PDF, Equivalent


Part Number

AS4LC4M4883C

Description

EDO PAGE MODE

Manufacture

ASI

Total Page 20 Pages
Datasheet
Download AS4LC4M4883C Datasheet


AS4LC4M4883C
www.DataSheet4U.com
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
DRAM
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE
AVAILABLE IN MILITARY
SPECIFICATIONS
• MIL-STD-883
• SMD Planned
PIN ASSIGNMENT (Top View)
24/28-Pin
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• Low power, 1mW standby; 150mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR)
HIDDEN
• 2,048-cycle (11 row-, 11 column-addresses)
• Extended Data-Out (EDO) PAGE access cycle
• 5V-tolerant I/Os (5.5V maximum VIH level)
OPTIONS
• Timing
60ns access (Contact Factory)
70ns acess
80ns access
• Packages
Ceramic SOJ
Ceramic LCC
Ceramic Gull Wing
KEY TIMING PARAMETERS
MARKING
-6
-7
-8
ECJ
EC
ECG
No. 505
No. 212
No. 603
SPEED
-6
-7
-8
tRC
110ns
130ns
150ns
tRAC
60ns
70ns
80ns
tPC
30ns
35ns
40ns
tAA
30ns
35ns
40ns
tCAC
15ns
18ns
20ns
tCAS
12ns
15ns
20ns
GENERAL DESCRIPTION
The AS4LC4M4 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. The AS4LC4M4 ?R?A/S is used to latch the first 11
bits and ?C?A/S the latter 11 bits. READ and WRITE cycles are
selected with the ?W/E input. A logic HIGH on
?W/E dictates READ mode while a logic LOW on ?W/E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of ?W/E or ?C?A/S, whichever occurs last. If
?W/E goes LOW prior to ?C?A/S going LOW, the output pins
remain open (High- Z) until the next ?C?A/S cycle, regardless
of ?O/E.
VCC
DQ1
DQ2
/W/E
/R/A/S
NC
A10
A0
A1
A2
A3
VCC
11
22
33
44
55
66
98
190
1110
1121
1132
1143
2268 VSS
2257 DQ4
2246 DQ3
2235 /C/A/S
2224 /O/E
2213 A9
1290 A8
1189 A7
1178 A6
1167 A5
1156 A4
1145 Vss
A logic HIGH on ?W/E dictates READ mode while a logic
LOW on ?W/E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of ?W/E or /C/A/S,
whichever occurs last. An EARLY WRITE occurs when
?W/E is taken LOW prior to /C/A/S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when ?W/E falls after /C/A/S
was taken LOW. During EARLY WRITE cycles, the data-
outputs (Q) will remain High-Z regardless of the state of
O? E/ . During LATE WRITE or READ-MODIFY-WRITE cycles,
?O/E must be taken HIGH to disable the data-outputs prior to
applying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping ?O/E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by ?W/E and ?O/E.
FAST PAGE MODE
FAST PAGE operations allow faster data operations
(READ, WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The FAST PAGE cycle is
always initiated with a row-address strobed-in by ?R?A/S
followed by a column-address strobed-inby C? ?A/S. ?C?A/S may
be toggled-in by holding ?R?A/S LOW and strobing-in differ-
ent column-addresses, thus executing faster memory cycles.
Returning R?A/S HIGH terminates the FAST PAGE MODE
of operation.
AS4LC4M4
Rev. 11/97
DS000022
2-73
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

AS4LC4M4883C
AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
EDO PAGE MODE
The AS4LC4M4E8 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?C?A/S returns HIGH. EDO allows ?C?A/S precharge time (tCP)
to occur without the output data going invalid. This elimi-
nation of ?C?A/S output control allows pipeline READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?C?A/S. EDO-PAGE-MODE DRAMs operate similarly to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after ?C?A/S goes HIGH during READs,
provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while
?R?A/S and ?C?A/S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If ?O/E is toggled or
pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW,
data will transition to and remain High-Z (refer to Figure 1).
?W/E can also perform the function of disabling the output
devices under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR’d,
?O/E must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing ?W/E to the idle banks during ?C?A/S high time
will also High-Z the outputs. Independent of ?O/E control,
the outputs will disable after tOFF, which is referenced
from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
RAS
V
V
IH
IL
CAS
V
V
IH
IL
,, ,,, ,,,,,,, ,,,,,,, ,,,,,, ,,,,,ADDR
V
V
IH
IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ
V IOH
V IOL
,,OPEN
VALID DATA (A)
tOD
tOES
VALID DATA (A)
,,,VALID DATA (B)
tOD
tOEHC
,,VALID DATA (C)
tOD
,VALID DATA (D)
OE
V IH
V IL
tOE
tOEP
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS cycle
if tOEHC is met.
Figure 1
OUTPUT ENABLE AND DISABLE
The DQs remain High-Z
until the next CAS cycle
if tOEP is met.
AS4LC4M4
Rev. 11/97
DS000022
2-74
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.


Features www.DataSheet4U.com AUSTIN SEMICONDUCTO R, INC. AS4LC4M4 883C 4 MEG x 4 DRAM DRAM AVAILABLE IN MILITARY SPECIFICATIO NS • MIL-STD-883 • SMD Planned 4 M EG x 4 DRAM 3.3V, EDO PAGE MODE PIN ASS IGNMENT (Top View) 24/28-Pin 1 1 2 2 3 3 4 4 5 5 6 6 9 8 10 9 11 10 12 11 13 1 2 14 13 28 26 27 25 26 24 25 23 24 22 2 3 21 20 19 19 18 18 17 17 16 16 15 15 1 4 VSS DQ4 DQ3 /C/A/S /O/E A9 A8 A7 A6 A 5 A4 Vss FEATURES • Industry-standar d x4 pinout, timing, functions and pack ages • High-performance CMOS silicon- gate process • Single +3.3V ± 0.3V p ower supply • Low power, 1mW standby; 150mW active, typical • All inputs, outputs and clocks are TTL-compatible Refresh modes: ?R?A/S ONLY, ?C?A/S-B EFORE-?R?A/S (CBR) HIDDEN • 2,048-cyc le (11 row-, 11 column-addresses) • E xtended Data-Out (EDO) PAGE access cycl e • 5V-tolerant I/Os (5.5V maximum VI H level) VCC DQ1 DQ2 /W/E /R/A/S NC A1 0 A0 A1 A2 A3 VCC OPTIONS • Timing 6 0ns access (Contact Factory) 70ns acess 80ns access • Packages Ceramic SOJ Ceramic LCC C.
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