AS4LC4M4F1 DRAM Datasheet

AS4LC4M4F1 Datasheet, PDF, Equivalent


Part Number

AS4LC4M4F1

Description

4M x 4 CMOS DRAM

Manufacture

Alliance Semiconductor

Total Page 14 Pages
Datasheet
Download AS4LC4M4F1 Datasheet


AS4LC4M4F1
www.DataSheet4U.com
May 2001
AS4LC4M4F1
®
4M×4 CMOS DRAM (Fast Page) 3.3V Family
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 500 mW max
- Standby: 3.6 mW max, CMOS I/O
• Fast page mode
• Refresh
- 2048 refresh cycles, 32 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
• 3.3V power supply
• Latch-up current 200 mA
• ESD protection 2000 volts
• Industrial and commercial temperature available
Pin arrangement
SOJ
TSOP*
VCC
I/O0
I/O1
WE
RAS
NC
1
2
3
4
5
6
26 GND
25 I/O3
24 I/O2
23 CAS
22 OE
21 A9
VCC
I/O0
I/O1
WE
RAS
NC
1
2
3
4
5
6
19 GND
18 I/O3
17 I/O2
16 CAS
15 OE
14 A9
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
19 A8
18 A7
17 A6
16 A5
15 A4
14 GND
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
*TSOP availability to be determined
Pin designation
Pin(s)
Description
A0 to A10
Address inputs
RAS Row address strobe
CAS Column address strobe
WE Write enable
I/O0 to I/O3
Input/output
OE Output enable
VCC
GND
Power
Ground
Selection guide
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
Maximum CMOS standby current
Symbol
tRAC
tCAA
tCAC
tOEA
tRC
tPC
ICC1
ICC5
AS4LC4M4F1-50
50
25
12
13
80
25
120
1.0
AS4LC4M4F1-60
60
30
15
15
100
30
110
1.0
Unit
ns
ns
ns
ns
ns
ns
mA
mA
5/16/01; v.1.0 Restored
Alliance Semiconductor
P. 1 of 14
Copyright © Alliance Semiconductor. All rights reserved.

AS4LC4M4F1
AS4LC4M4F1
®
Functional description
The AS4LC4M4F1 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 4,194,304
words × 4 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed,
extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as
main memory in PC, workstation, router and switch applications.
This device features a high speed page-mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The AS4LC4M4F1 is available in the standard 24/26-pin plastic SOJ. TSOP 24/26-pin availability is to be determined. The AS4LC4M4F1
operates with a single power supply of 3.3V ± 0.3V and provides TTL compatible inputs and outputs.
Logic block diagram for 2K refresh
VCC
GND
RAS
CAS
WE
RAS clock
generator
CAS clock
generator
WE clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Column decoder
Sense amp
2048 × 2048 × 4
Array
(16,777,216)
Data
I/O
buffers
I/O0 to I/O3
OE
Substrate bias
generator
Recommended operating conditions
Parameter
Symbol Min Nominal Max
Supply voltage
VCC 3.0 3.3 3.6
GND 0.0 0.0 0.0
Input voltage
VIH 2.0
VIL –0.5
– VCC+0.5V
– 0.8
Commercial
0 – 70
Ambient operating temperature
Industrial
TA
-40
85
VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
Unit
V
V
V
V
°C
5/16/01; v.1.0 Restored
Alliance Semiconductor
P. 2 of 14


Features www.DataSheet4U.com May 2001 ® AS4LC4 M4F1 4M×4 CMOS DRAM (Fast Page) 3.3V Family Features • Organization: 4,194 ,304 words × 4 bits • High speed - 5 0/60 ns RAS access time - 25/30 ns colu mn address access time - 12/15 ns CAS a ccess time • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-on ly or CAS-before-RAS refresh or self-re fresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mi l, 24/26-pin SOJ • Low power consump tion - Active: 500 mW max - Standby: 3. 6 mW max, CMOS I/O • Fast page mode • 3.3V power supply • Latch-up cur rent ≥ 200 mA • ESD protection ≥ 2000 volts • Industrial and commercia l temperature available Pin arrangemen t SOJ VCC I/O0 I/O1 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 GND I/O3 I/O2 CAS OE A9 A8 A7 A6 A5 A4 GND VCC I/O0 I/O1 WE RAS NC A10 A0 A1 A2 A 3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 Pin designation TSOP* 19 18 17 16 15 14 26 25 24 23 22 21 GND I/O3 I/O2 CAS OE A9 A8 A7 A6 A5 A4.
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