IS25C01 PROM Datasheet

IS25C01 Datasheet, PDF, Equivalent


Part Number

IS25C01

Description

1K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

Manufacture

ISSI

Total Page 17 Pages
Datasheet
Download IS25C01 Datasheet


IS25C01
www.DataSheet4U.com
IS25C01
1K-BIT SPI SERIAL
ELECTRICALLY ERASABLE PROM
ISSI®
Preliminary Information
January 2006
FEATURES
• Serial Peripheral Interface (SPI) Compatible
— Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low-voltage Operation
— Vcc = 1.8V to 5.5V
• Low power CMOS
— Active current less than 3.0 mA (2.5V)
— Standby current less than 1 µA (2.5V)
• Block Write Protection
— Protect 1/4, 1/2, or Entire Array
• 8bytepagewritemode
— Partial page writes allowed
• 10 MHz Clock Rate (5V)
• Self timed write cycles
— 5 ms max. @ 2.5V
• High-reliability
— Endurance: 1 million cycles per byte
— Data retention: 100 years
• 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP packages
are available
• Lead-free available
DESCRIPTION
The IS25C01 is an electrically erasable PROM device
that uses the Serial Peripheral Interface (SPI) for
communications. The IS25C01 is 1Kbit
(128 x 8). The IS25C01 EEPROM is offered in a wide
operating voltage range of 1.8V to 5.5V to be compatible
with most application voltages. ISSI designed the
IS25C01 to be an efficient SPI EEPROM solution. The
device is packaged in 8-pin PDIP, 8-pin SOIC, and 8-pin
TSSOP.
The functional features of the IS25C01 allow it to be
among the most versatile serial non-volatile memories
available. Each device has a Chip-Select (CS) pin, and
a 3-wire interface of Serial Data In (SI), Serial Data Out
(SO), and Serial Clock (SCK). While the 3-wire inter-
face of the IS25C01 provides for high-speed access, a
HOLD pin allows the memories to ignore the interface in
a suspended state; later the HOLD pin re-activates
communication without re-initializing the serial se-
quence. A Status Register facilitates a flexible write
protection mechanism, and a device-ready bit (RDY).
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05
1

IS25C01
IS25C01
PIN CONFIGURATION
8-Pin DIP, TSSOP, and SOIC
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
ISSI ®
PIN DESCRIPTIONS
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power
Write Protect
Suspends Serial Input
No Connect
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides syn-
chronization between the microcontroller and IS25C01.
Op-Codes, byte addresses, and data are latched on SI
with a rising edge of the SCK. Data on SO is refreshed
on the falling edge of SCK for SPI modes (0,0) and (1,1).
Serial Data Input (SI): This is the input pin for all data
that the IS25C01 is required to receive.
Serial Data Output (SO): This is the output pin for all
data transmitted from the IS25C01.
Chip Select (CS): The CS pin activates the device.
Upon power-up, CS should follow Vcc. When the device
is to be enabled for instruction input, the signal requires
a High-to-Low transition. While CS is stable Low, the
master and slave will communicate via SCK, SI, and SO
signals. Upon completion of communication, CS must
be driven High. At this moment, the slave device may
start its internal write cycle. When CS is high, the
device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.
Write Protect (WP): The purpose of this input signal is
to initiate Hardware Write Protection mode. This mode
prevents the 128 byte array or the Status Register from
being altered. To cause Hardware Write Protection, WP
must be Low. WP may be hardwired to Vcc or GND.
HOLD (HOLD): This input signal is used to suspend the
device in the middle of a serial sequence and temporarily
ignore further communication on the bus (SI, SO, SCK).
Together with Chip Select, the HOLD signal allows
multiple slaves to share the bus. The HOLD signal
transitions must occur only when SCK is Low, and be
held stable during SCK transitions. (See Figure 8 for
Hold timing) To disable this feature, HOLD may be
hardwired to Vcc.
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Preliminary Information Rev. 00B
12/23/05


Features www.DataSheet4U.com IS25C01 1K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM ISSI Preliminary Information January 2006 ® FEATURES • Serial Peripheral Inte rface (SPI) Compatible — Supports SPI Modes 0 (0,0) and 3 (1,1) • Low-volt age Operation — Vcc = 1.8V to 5.5V Low power CMOS — Active current les s than 3.0 mA (2.5V) — Standby curren t less than 1 µA (2.5V) • Block Writ e Protection — Protect 1/4, 1/2, or E ntire Array • 8 byte page write mode — Partial page writes allowed • 10 MHz Clock Rate (5V) • Self timed writ e cycles — 5 ms max. @ 2.5V • High- reliability — Endurance: 1 million cy cles per byte — Data retention: 100 y ears • 8-pin PDIP, 8-pin SOIC, and 8- pin TSSOP packages are available • Le ad-free available DESCRIPTION The IS25 C01 is an electrically erasable PROM de vice that uses the Serial Peripheral In terface (SPI) for communications. The I S25C01 is 1Kbit (128 x 8). The IS25C01 EEPROM is offered in a wide operating voltage range of 1.8V to 5.5V to be compatible with most applicat.
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