Sync FIFOs. CY7C4292 Datasheet

CY7C4292 FIFOs. Datasheet pdf. Equivalent


Cypress Semiconductor CY7C4292
www.DataSheet4U.com
CY7C4282
CY7C4292
Features
64K/128K x 9 Deep Sync FIFOs with
Retransmit and Depth Expansion
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64K × 9 (CY7C4282)
• 128K × 9 (CY7C4292)
• 0.5-micron CMOS for optimum speed/power
• High-speed, near-zero latency (true dual-ported
memory cell), 100-MHz operation (10-ns read/write
cycle times)
• Low power
ICC=40 mA
ISB = 2 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL-compatible
• Retransmit function
Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Depth-Expansion Capability through token-passing
scheme (no external logic required)
• 64-pin 10 × 10 STQFP
The CY7C4282/CY7C4292 are high-speed, low-power, FIFO
memories with clocked read and write interfaces. All devices
are nine bits wide. The CY7C4282/CY7C4292 can be
cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, video
and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a
write-enable pin (WEN).
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (XI),
cascade output (XO), and First Load (FL) pins. The XO pin is
connected to the XI pin of the next device, and the XO pin of
the last device should be connected to the XI pin of the first
device. The FL pin of the first device is tied to VSS and the FL
pin of all the remaining devices should be tied to VCC.
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN). In addition, the
CY7C4282/92 have an output enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
Logic Block Diagram
D0-8
INPUT
REGISTER
WCLK WEN
WRITE
CONTROL
RS
FL/RT
XI/LD
PAF/XO
WRITE
POINTER
RESET
LOGIC
EXPANSION
LOGIC
Dual Port
RAM Array
64K x 9
128K x 9
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
FF
EF
PAE
PAF/XO
THREE-STATE
OUTPUT REGISTER
Q0 8
OE
READ
CONTROL
RCLK REN
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06009 Rev. *B
Revised August 21, 2003


CY7C4292 Datasheet
Recommendation CY7C4292 Datasheet
Part CY7C4292
Description (CY7C4282 / CY7C4292) 64K/128K x 9 Deep Sync FIFOs
Feature CY7C4292; www.DataSheet4U.com CY7C4282 CY7C4292 64K/128K x 9 Deep Sync FIFOs with Retransmit and Depth Expan.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C4292 Datasheet




Cypress Semiconductor CY7C4292
Pin Configuration
STQFP
Top View
WEN
RS
D8
D7
D6
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D5
D4
D3
D2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4282
CY7C4292
48 Q5
47 Q4
46 GND
45 Q3
44 Q2
43 VCC
42 Q1
41 Q0
40 GND
39 N/C
38 FF
37 EF
36 OE
35 GND
34 FL/RT
33 N/C
CY7C4282
CY7C4292
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current (ICC)
Commercial
Industrial
7C4282/92-10
100
8
10
3
0.5
8
40
45
7C4282/92-15
66.7
10
15
4
1
10
40
7C4282/92-25
40
15
25
6
1
15
40
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
CY7C4282
64k x 9
64-pin 10x10 STQFP
CY7C4292
128k x 9
64-pin 10x10 STQFP
Pin Definitions
Signal
Name
D0 8
Q0 8
WEN
Description
Data Inputs
Data Outputs
Write Enable
REN
Read Enable
WCLK Write Clock
I/O Description
I Data Inputs for 9-bit bus.
O Data Outputs for 9-bit bus.
I The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
I Enables the device for Read operation. REN must be asserted LOW to allow a read
operation.
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When
LD is asserted, WCLK writes data into the programmable flag-offset register.
Document #: 38-06009 Rev. *B
Page 2 of 16



Cypress Semiconductor CY7C4292
CY7C4282
CY7C4292
Pin Definitions
Signal
Name
RCLK
EF
FF
PAE
PAF/XO
FL/RT
XI/LD
OE
RS
Description I/O
Description
Read Clock
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
When LD is LOW, RCLK reads data out of the programmable flag-offset register.
Empty Flag
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
Full Flag
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is synchronized to RCLK.
Programmable O Dual-Mode Pin. Cascaded – Connected to XI of next device. Not Cascaded – When PAF is
Almost Full/
LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO.
Expansion Output PAF is synchronized to WCLK.
First Load/
Retransmit
I Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to VSS; all
other devices will have FL tied to VCC. In standard mode or width expansion, FL is tied
to VSS on all devices. Not Cascaded – Retransmit function is available in stand-alone mode
by strobing RT.
Expansion
Input/Load
I Dual-Mode Pin. Cascaded – Connected to XO of previous device. Not Cascaded – LD is
used to write or read the programmable flag offset registers. LD must be asserted low during
reset to enable standalone or width expansion operation. If programmable offset register
access is not required, LD can be tied to RS directly.
Output Enable
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Reset
I Resets device to empty condition. A reset is required before an initial read or write operation
after power-up.
Functional Description (continued)
The CY7C4282/92 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty+7 and Full-7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Architecture
The CY7C4282/92 consists of an array of 64K to 128K words
of 9 bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q08) go LOW
tRSF after the rising edge of RS. In order for the FIFO to reset
to its default state, the user must not read or write while RS is
LOW. All flags are guaranteed to be valid tRSF after RS is taken
LOW.
During reset of the FIFO, the state of the XI/LD pin determines
if depth expansion operation is used. For depth expansion
operation, XI/LD is tied to XO of the next device. See “Depth
Expansion Configuration” and Figure 3. For standalone or
width-expansion configuration, the XI/LD pin must be asserted
low during reset.
There is a 0-ns hold time requirement for the XI/LD configu-
ration at the RS deassertion edge. This allows the user to tie
XI/LD to RS directly for applications that do not require access
to the flag offset registers.
FIFO Operation
When the WEN is asserted LOW and FF is HIGH, data present
on the D0–8 pins is written into the FIFO on each rising edge
of the WCLK signal. Similarly, when the REN is asserted LOW
and EF is HIGH, data in the FIFO memory will be presented
on the Q0–8 outputs. New data will be presented on each rising
edge of RCLK while REN is active. REN must set up tENS
before RCLK for it to be a valid read function. WEN must occur
tENS before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–8 outputs
after tOE. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–8 outputs
even after additional reads occur.
Document #: 38-06009 Rev. *B
Page 3 of 16







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