Sync FIFOs. CY7C4292V Datasheet
64K/128Kx9 Low Voltage Deep Sync FIFOs
w/ Retransmit & Depth Expansion
• 3.3V operation for low power consumption and easy
integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO)
• 64K x 9 (CY7C4282V)
• 128K x 9 (CY7C4292V)
• 0.35 micron CMOS for optimum speed/power
• High-speed, Near Zero Latency (True Dual-Ported
Memory Cell), 100-MHz operation (10 ns read/write
• Low power
— ICC = 25 mA
— ISB = 6 mA
• Fully asynchronous and simultaneous read and write
• Empty, Full, and Programmable Almost Empty and Al-
most Full status flags
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability through token-passing
scheme (no external logic required)
• 64-pin 10x10 STQFP
• Pin-compatible 3.3V solution for CY7C4282/92
The CY7C4282V/92V are high-speed, low-power, first-in first-
out (FIFO) memories with clocked read and write interfaces.
All devices are 9 bits wide. The CY7C4282V/92V can be cas-
caded to increase FIFO depth. Programmable features include
Almost Full/Almost Empty flags. These FIFOs provide solutions
for a wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, video and communications
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a Write Enable
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (XI), Cas-
cade Output (XO), and First Load (FL) pins. The XO pin is connected
to the XI pin of the next device, and the XO pin of the last device
should be connected to the XI pin of the first device. The FL pin of the
first device is tied to VSS and the FL pin of all the remaining devices
should be tied to VCC
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C4282V/92V have an Output Enable pin (OE). The read
and write clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 67 MHz are
Logic Block Diagram
D0 − 8
64K x 9
128K x 9
Q0 − 8
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 18, 1999
Functional Description (continued)
The CY7C4282V/92V provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to sin-
gle word granularity. The programmable flags default to Emp-
ty+7 and Full−7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (ICC) (mA)
64k x 9
64-pin 10x10 TQFP
128k x 9
64-pin 10x10 TQFP
I Data Inputs for 9-bit bus.
O Data Outputs for 9-bit bus.
I The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
I Enables the device for Read operation. REN must be asserted LOW to allow a Read
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
When LD is LOW, RCLK reads data out of the programmable flag-offset register.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO. PAE is synchronized to RCLK.
O Dual-Mode Pin:
Cascaded - Connected to XI of next device.
Not Cascaded - When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
I Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to VSS; all other devices
will have FL tied to VCC. In standard mode or width expansion, FL is tied to VSS
on all devices.
Not Cascaded - Retransmit function is available in stand-alone mode by strobing
I Dual-Mode Pin:
Cascaded - Connected to XO of previous device.
Not Cascaded - LD is used to write or read the programmable flag offset registers. LD
must be asserted LOW during reset to enable standalone or width expansion operation.
If programmable offset register access is not required, LD can be tied to RS directly.
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connect-
ed. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
I Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ....................................... −65°C to +150°C
Ambient Temperature with
Power Applied .................................................... −55°C to +125°C
Supply Voltage to Ground Potential..........−0.5V to VCC +0.5V
DC Voltage Applied to Outputs
in High Z State ..............................................−0.5V to VCC+0.5V
DC Input Voltage .........................................−0.5V to VCC +0.5V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
0°C to +70°C
−40°C to +85°C
3.3V + /−300mV
3.3V + /−300mV
1. TA is the “instant on” case temperature.
2. VCC Range for commercial -10 ns is 3.3V ± 150 mV.