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CY7C4292V Dataheets PDF



Part Number CY7C4292V
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C4282V / CY7C4292V) 64K/128Kx9 Low Voltage Deep Sync FIFOs
Datasheet CY7C4292V DatasheetCY7C4292V Datasheet (PDF)

www.DataSheet4U.com CY7C4282V CY7C4292V 64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion Features • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • 64K x 9 (CY7C4282V) • 128K x 9 (CY7C4292V) • 0.35 micron CMOS for optimum speed/power • High-speed, Near Zero Latency (True Dual-Ported Memory Cell), 100-MHz operation (10 ns read/write cycle times) • Low power — ICC = 25 mA • .

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www.DataSheet4U.com CY7C4282V CY7C4292V 64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion Features • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • 64K x 9 (CY7C4282V) • 128K x 9 (CY7C4292V) • 0.35 micron CMOS for optimum speed/power • High-speed, Near Zero Latency (True Dual-Ported Memory Cell), 100-MHz operation (10 ns read/write cycle times) • Low power — ICC = 25 mA • • • • • • • • • • — ISB = 6 mA Fully asynchronous and simultaneous read and write operation Empty, Full, and Programmable Almost Empty and Almost Full status flags Retransmit function Output Enable (OE ) pin Independent read and write enable pins Supports free-running 50% duty cycle clock inputs Width Expansion Capability Depth Expansion Capability through token-passing scheme (no external logic required) 64-pin 10x10 STQFP Pin-compatible 3.3V solution for CY7C4282/92 Functional Description The CY7C4282V/92V are high-speed, low-power, first-in firstout (FIFO) memories with clocked read and write interfaces. All devices are 9 bits wide. The CY7C4282V/92V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a Write Enable pin (WEN). Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the Cascade Input (XI), Cascade Output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running Read Clock (RCLK) and a Read Enable pin (REN). In addition, the CY7C4282V/92V have an Output Enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 67 MHz are achievable. D0 − 8 Logic Block Diagram INPUT REGISTER WCLK WEN FLAG PROGRAM REGISTER WRITE CONTROL FF FLAG LOGIC Dual Port RAM Array 64K x 9 128K x 9 READ POINTER EF PAE PAF/XO WRITE POINTER RS RESET LOGIC FL/RT XI/LD PAF/XO EXPANSION LOGIC THREE-STATE OUTPUT REGISTER OE Q0 − 8 READ CONTROL RCLK REN 4282V–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 18, 1999 CY7C4282V CY7C4292V Pin Configuration WCLK XI/LD GND N/C N/C N/C N/C N/C VCC N/C N/C Q8 Q7 GND Q6 N/C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 STQFP Top View 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 WEN RS D8 D7 D6 N/C N/C N/C N/C N/C N/C N/C D5 D4 D3 D2 CY7C4282V CY7C4292V Q5 Q4 GND Q3 Q2 VCC Q1 Q0 GND N/C FF EF OE GND FL/RT N/C 4282V–2 Functional Description (continued) The CY7C4282V/92V provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty+7 and Full−7. The flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When Selection Guide 7C4282V/92V-10 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC) (mA) Commercial Industrial 100 8 10 3.5 0 8 25 7C4282V/92V-15 66.7 10 15 4 0 10 25 30 7C4282V/92V-25 40 15 25 6 1 15 25 D1 D0 N/C N/C N/C VCC PAF/XO PAE N/C N/C N/C N/C N/C GND REN RCLK entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle All configurations are fabricated using an advanced 0.35µ CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. CY7C4282V Density Package 64k x 9 64-pin 10x10 TQFP CY7C4292V 128k x 9 64-pin 10x10 TQFP 2 CY7C4282V CY7C4292V Pin Definitions Signal Name D0−8 Q0−8 WEN REN WCLK RCLK EF FF .


CY7C4282V CY7C4292V EZ80F92


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