Data Recovery. ADN2807 Datasheet

ADN2807 Recovery. Datasheet pdf. Equivalent


Analog Devices ADN2807
www.DataSheet4U.com
155/622 Mb/s Clock and Data Recovery IC
with Integrated Limiting Amp
ADN2807
FEATURES
Meets SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss-of-signal detect range: 3 mV to 15 mV
Single-reference clock frequency for all rates, including
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or
155.52 MHz REFCLK
REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible
(LVPECL/LVDS only at 155.52 MHz)
Optional 19.44 MHz on-chip oscillator to be used with
external crystal
Loss-of-lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm, 48-lead LFCSP
GENERAL DESCRIPTION
The ADN2807 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at rates of OC-3,
OC-12, and 15/14 FEC. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance. All
specifications are quoted for –40°C to +85°C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both native rates and 15/14 rate
digital wrappers are supported by the ADN2807, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
APPLICATIONS
SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates
WDM transponders
The ADN2807 is available in a compact 7 mm × 7 mm 48-lead
chip-scale package (LFCSP).
Regenerators/repeaters
Test equipment
Passive optical networks
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC VEE
CF1 CF2
LOL
2 ADN2807
PIN
QUANTIZER
NIN
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
VREF
LEVEL
DETECT
THRADJ SDOUT
DATA
RETIMING
2
DATAOUTP/N
DIVIDER
1/2/4/16
2
CLKOUTP/N
FRACTIONAL
DIVIDER
3
SEL[0..2]
2
2
/n
XTAL
OSC
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.


ADN2807 Datasheet
Recommendation ADN2807 Datasheet
Part ADN2807
Description Clock and Data Recovery
Feature ADN2807; www.DataSheet4U.com 155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2807 FE.
Manufacture Analog Devices
Datasheet
Download ADN2807 Datasheet




Analog Devices ADN2807
www.DataSheet4U.com
ADN2807
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Definition of Terms .......................................................................... 8
Maximum, Minimum, and Typical Specifications ................... 8
Input Sensitivity and Input Overdrive....................................... 8
Single-Ended vs. Differential ...................................................... 8
LOS Response Time ..................................................................... 9
Jitter Specifications....................................................................... 9
Theory of Operation ...................................................................... 10
Functional Description .................................................................. 12
Multirate Clock and Data Recovery......................................... 12
REVISION HISTORY
5/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Specifications ............................................................ 3
Change to Table 7 and Table 8 .................................................. 13
1/04—Revision 0: Initial Version
Limiting Amplifier ..................................................................... 12
Slice Adjust .................................................................................. 12
Loss-of-Signal (LOS) Detector ................................................. 12
Reference Clock.......................................................................... 12
Lock Detector Operation .......................................................... 13
Squelch Mode ............................................................................. 14
Test Modes—Bypass and Loop-back....................................... 14
Application Information................................................................ 15
PCB Design Guidelines ............................................................. 15
Choosing AC Coupling Capacitors.......................................... 17
DC-Coupled Application .......................................................... 17
LOL Toggling during Loss of Input Data................................ 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
Rev. A | Page 2 of 20



Analog Devices ADN2807
www.DataSheet4U.com
ADN2807
SPECIFICATIONS
Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 4.7 µF, SLICEP = SLICEN = VCC, unless otherwise noted
Parameter
Conditions
Min Typ
Max Unit
QUANTIZER–DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
0
1.2 V
Peak-to-Peak Differential Input
2.4 V
Input Common-Mode Level
Differential Input Sensitivity
DC-coupled (See Figure 26)
0.4
PIN−NIN, ac-coupled1, BER = 1 × 10–10
4
V
10 mV p-p
Input Overdrive
Input Offset
Input RMS Noise
See Figure 8
BER = 1 × 10–10
25
500
244
mV p-p
µV
µV rms
QUANTIZER–AC CHARACTERISTICS
Small Signal Gain
Input Resistance
Input Capacitance
Pulse-Width Distortion2
Differential
Differential
54 dB
100 Ω
0.65 pF
10 ps
QUANTIZER SLICE ADJUSTMENT
Gain
SliceP – SliceN = ±0.5 V
0.11 0.20
0.30 V/V
Control Voltage Range
SliceP – SliceN
–0.8 +0.8 V
@ SliceP or SliceN
1.3 VCC V
Slice Threshold Offset
±1.0 mV
LEVEL SIGNAL DETECT (SDOUT)
Level Detect Range (See Figure 4)
Response Time
RTHRESH = 2 kΩ
RTHRESH = 20 kΩ
RTHRESH = 90 kΩ
DC-coupled
9.4 13.3 18.0 mV
2.5 5.3
7.6 mV
0.7 3.0
5.2 mV
0.1 0.3
5
µs
Hysteresis (Electrical)
OC-12, PRBS 223
RTHRESH = 2 kΩ
RTHRESH = 20 kΩ
RTHRESH = 90 kΩ
RTHRESH = 90 kΩ @ 25°C
OC-3, PRBS 223
4.7 6.4
1.8 6.0
6.3
4.8 6.9
7.8 dB
10.0 dB
dB
8.9 dB
RTHRESH = 2 kΩ
RTHRESH = 20 kΩ
RTHRESH = 90 kΩ
RTHRESH = 90 k @ 25°C
OC-12, PRBS 27
RTHRESH = 2 kΩ
RTHRESH = 20 kΩ
RTHRESH = 90 kΩ
OC-3, PRBS 27
3.6 6.2
5.6
5.6
3.4 6.6
5.7 6.6
3.9 6.2
3.2 6.7
8.5 dB
dB
dB
9.9 dB
7.8 dB
8.5 dB
9.9 dB
LOSS-OF-LOCK DETECTOR (LOL)
RTHRESH = 2 kΩ
RTHRESH = 20 kΩ
RTHRESH = 90 kΩ
5.4 6.6
4.6 6.4
3.9 6.8
7.7 dB
8.2 dB
9.7 dB
Loss-of-Lock Response Time
POWER SUPPLY VOLTAGE
From fVCO error > 1000 ppm
60
3.0 3.3
mV
3.6 V
POWER SUPPLY CURRENT
150 164
215 mA
Rev. A | Page 3 of 20





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