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ADN2807 Dataheets PDF



Part Number ADN2807
Manufacturers Analog Devices
Logo Analog Devices
Description Clock and Data Recovery
Datasheet ADN2807 DatasheetADN2807 Datasheet (PDF)

www.DataSheet4U.com 155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2807 FEATURES Meets SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including 15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK REFCLK inputs: LVPECL/LVDS/LVCMO.

  ADN2807   ADN2807



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www.DataSheet4U.com 155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2807 FEATURES Meets SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including 15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible (LVPECL/LVDS only at 155.52 MHz) Optional 19.44 MHz on-chip oscillator to be used with external crystal Loss-of-lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation: 3.3 V Low power: 540 mW typical 7 mm × 7 mm, 48-lead LFCSP GENERAL DESCRIPTION The ADN2807 provides the receiver functions of quantization, signal level detect, and clock and data recovery at rates of OC-3, OC-12, and 15/14 FEC. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for –40°C to +85°C ambient temperature, unless otherwise noted. The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both native rates and 15/14 rate digital wrappers are supported by the ADN2807, without any change of reference clock. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver. The receiver front end signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output. The ADN2807 is available in a compact 7 mm × 7 mm 48-lead chip-scale package (LFCSP). APPLICATIONS SONET OC-3/-12, SDH STM-1/-4 and, 15/14 FEC rates WDM transponders Regenerators/repeaters Test equipment Passive optical networks FUNCTIONAL BLOCK DIAGRAM SLICEP/N VCC VEE CF1 CF2 LOL 2 PIN QUANTIZER NIN ADN2807 LOOP FILTER /n XTAL OSC 2 2 REFSEL[0..1] REFCLKP/N XO1 PHASE SHIFTER PHASE DET. LOOP FILTER VCO FREQUENCY LOCK DETECTOR XO2 VREF LEVEL DETECT DATA RETIMING 2 THRADJ SDOUT DATAOUTP/N 2 CLKOUTP/N SEL[0..2] DIVIDER 1/2/4/16 FRACTIONAL DIVIDER 3 REFSEL 03877-0-001 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 .


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