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ADN2804 Dataheets PDF



Part Number ADN2804
Manufacturers Analog Devices
Logo Analog Devices
Description Clock and Data Recovery
Datasheet ADN2804 DatasheetADN2804 Datasheet (PDF)

www.DataSheet4U.com 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier ADN2804 FEATURES Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operat.

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www.DataSheet4U.com 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier ADN2804 FEATURES Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 423 mW typical 5 mm × 5 mm, 32-lead LFCSP, Pb free GENERAL DESCRIPTION The ADN2804 provides the receiver functions of quantization, signal level detect, clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2804 automatically locks to 622 Mbps data without the need for an external reference clock or programming. In the absence of input data, the output clock drifts no more than ±5%. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver’s front-end loss-of-signal (LOS) detector circuit indicates when the input signal level falls below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2804 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. APPLICATIONS BPON ONT SONET OC-12 WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN (OPTIONAL) LOL CF1 CF2 VCC VEE SLICEP/SLICEN PIN NIN 2 FREQUENCY DETECT LOOP FILTER QUANTIZER PHASE SHIFTER PHASE DETECT LOOP FILTER VCO VREF LOS DETECT DATA RE-TIMING 2 2 THRADJ LOS DATAOUTP/ DATAOUTN CLKOUTP/ CLKOUTN ADN2804 05801-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. www.DataSheet4U.com ADN2804 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Jitter Specifications....................................................................... 4 Output and Timing Specifications ............................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Timing Characteristics..................................................................... 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 I2C Interface Timing and Internal Register Description........... 10 Terminology .................................................................................... 12 Jitter Specifications......................................................................... 13 Theory of Operation ...................................................................... 14 Functional Description.................................................................. 16 Frequency Acquisition............................................................... 16 Limiting Amplifier ..................................................................... 16 Slice Adjust.................................................................................. 16 Loss-of-Signal (LOS) Detector ................................................. 16 Lock Detector Operation .......................................................... 17 SQUELCH Modes ...................................................................... 17 I2C Interface ....................


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