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MT5C6401 Dataheets PDF



Part Number MT5C6401
Manufacturers Micron Technology
Logo Micron Technology
Description 64K x 1 SRAM
Datasheet MT5C6401 DatasheetMT5C6401 Datasheet (PDF)

www.DataSheet4U.com OBSOLETE 8/31/94 MT5C6401 64K x 1 SRAM SRAM FEATURES • High speed: 9, 10, 12, 15, 20 and 25ns • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Easy memory expansion with /C/E option • All inputs and outputs are TTL-compatible 64K x 1 SRAM PIN ASSIGNMENT (Top View) 22-Pin DIP (SA-2) A0 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 Vcc A15 A14 A13 A12 A11 A10 A9 A8 D CE OPTIONS • Timing 9ns access 10ns access 12ns access .

  MT5C6401   MT5C6401



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www.DataSheet4U.com OBSOLETE 8/31/94 MT5C6401 64K x 1 SRAM SRAM FEATURES • High speed: 9, 10, 12, 15, 20 and 25ns • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Easy memory expansion with /C/E option • All inputs and outputs are TTL-compatible 64K x 1 SRAM PIN ASSIGNMENT (Top View) 22-Pin DIP (SA-2) A0 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 Vcc A15 A14 A13 A12 A11 A10 A9 A8 D CE OPTIONS • Timing 9ns access 10ns access 12ns access 15ns access 20ns access 25ns access • Packages Plastic DIP (300 mil) Plastic SOJ (300 mil) • 2V data retention • Temperature Commercial Industrial Automotive Extended MARKING - 9 -10 -12 -15 -20 -25 A1 A2 A3 A4 A5 A6 A7 Q None DJ L WE Vss 24-Pin SOJ (SD-1) A0 A1 A2 A3 A4 A5 NC A6 A7 Q WE Vss 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Vcc A15 A14 A13 A12 NC A11 A10 A9 A8 D CE (0°C to +70°C) (-40°C to +85°C) (-40°C to +125°C) (-55°C to +125°C) None IT AT XT • Part Number Example: MT5C6401DJ-10 L NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availability of specific part number combinations. GENERAL DESCRIPTION The MT5C6401 is organized as a 65,556 x 1 SRAM using a four-transistor memory cell with a high-speed, low-power CMOS process. Micron SRAMs are fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Micron offers chip enable (/C/E) with all organizations. This enhancement can place the outputs in High-Z for additional flexibility in system design. The x1 configuration features separate data input and output. MT5C6401 REV. 12/93 Writing to these devices is accomplished when write enable (?W/E) and /C/E inputs are both LOW. Reading is accomplished when ?W/E remains HIGH and /C/E goes to LOW. The device offers a reduced power standby mode when disabled. This allows system designers to meet low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL-compatible. 1 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. ©1993, Micron Semiconductor, Inc. OBSOLETE 8/31/94 MT5C6401 64K x 1 SRAM FUNCTIONAL BLOCK DIAGRAM Vcc GND A A A A A A 65,536-BIT MEMORY ARRAY I/O CONTROL A ROW DECODER D Q CE (LSB) WE COLUMN DECODER (LSB) POWER DOWN A A A A A A A TRUTH TABLE MODE STANDBY READ WRITE /C/E H L L ?W/E X H L INPUT DON’T CARE DON’T CARE DATA-IN OUTPUT HIGH-Z Q HIGH-Z POWER STANDBY ACTIVE ACTIVE MT5C6401 REV. 12/93 2 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. ©1993, Micron Semiconductor, Inc. OBSOLETE 8/31/94 MT5C6401 64K x 1 SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Supply Relative to VSS .............. -1V to +7V Storage Temperature (plastic) .................... -55°C to +15.


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