SHARC Processor. ADSP-21375 Datasheet

ADSP-21375 Processor. Datasheet pdf. Equivalent


Analog Devices ADSP-21375
SHARC Processor
ADSP-21371/ADSP-21375
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Order-
ing Guide on Page 56.
DEDICATED AUDIO COMPONENTS
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 33 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in a 208-lead LQFP_EP package
SIMD Core
Instruction
Cache
5 stage
Sequencer
DAG1/2
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
S
DMD 64-BIT
PMD 64-BIT
Core Bus
Cross Bar
DMD 64-BIT
PMD 64-BIT
PERIPHERAL BUS
32-BIT
EPD BUS 48-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
Internal Memory I/F
IODO 32-BIT
IOD1
32-BIT
PERIPHERAL BUS
IOD0 BUS
MTM/
D TCP
EP
CORE PCG TIMER
FLAGS C-D
1-0 TWI SPI/B UART
PCG S/PDIF IDP/ SPORT
A-D Tx/Rx PDAP 7-0
7-0
CORE PWM
FLAGS 3-0
AMI SDRAM
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
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Rev. D
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ADSP-21375 Datasheet
Recommendation ADSP-21375 Datasheet
Part ADSP-21375
Description SHARC Processor
Feature ADSP-21375; SHARC Processor ADSP-21371/ADSP-21375 SUMMARY High performance 32-bit/40-bit floating point process.
Manufacture Analog Devices
Datasheet
Download ADSP-21375 Datasheet




Analog Devices ADSP-21375
ADSP-21371/ADSP-21375
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 6
I/O Processor Features ......................................... 10
System Design .................................................... 10
Development Tools ............................................. 11
Additional Information ........................................ 12
Related Signal Chains .......................................... 12
Pin Function Descriptions ....................................... 13
ADSP-21371/ADSP-21375 Specifications .................... 16
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 17
Package Information ............................................ 18
Maximum Power Dissipation ................................. 18
Absolute Maximum Ratings ................................... 18
ESD Sensitivity ................................................... 18
Timing Specifications ........................................... 18
Output Drive Currents ......................................... 49
Test Conditions .................................................. 49
Capacitive Loading .............................................. 49
Thermal Characteristics ........................................ 50
208-Lead LQFP_EP Pinout ....................................... 51
Package Dimensions ............................................... 55
Automotive Products .............................................. 56
Ordering Guide ..................................................... 56
REVISION HISTORY
4/13—Rev. C to Rev. D
Corrected Extended Precision Normal or Instruction Word
(48 bits) ADSP-21375 Internal Memory Space .................7
Updated Development Tools ..................................... 11
Added section Related Signal Chains ...........................12
Revised MS1-0 pin description in
Pin Function Descriptions ........................................ 13
Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in
Pin Function Descriptions ........................................ 13
Corrected TJUNCTION specifications in
Operating Conditions .............................................. 16
Added footnote 3 to Table 25 in
Memory Read—Bus Master ....................................... 29
Updated Serial Ports timing parameter data in Serial Ports—
External Clock ....................................................... 33
Updated Serial Ports timing parameter data in Serial Ports—
Internal Clock ........................................................ 34
Changed Max values in Table 33 in Pulse-Width Modulation
Generators (PWM) ................................................. 40
Updated timing parameters in Table 37 and in Figure 31 in
SPI Interface—Master .............................................. 44
Added 1.0 V, 200 MHz specifications to the following timing
specifications.
Clock Input ............................................................21
Precision Clock Generator (Direct Pin Routing) .............26
SDRAM Interface Timing ..........................................28
Memory Read—Bus Master .......................................29
Memory Write—Bus Master ......................................31
Serial Ports ............................................................33
Input Data Port (IDP) ..............................................38
S/PDIF Transmitter Input Data Timing ........................42
S/PDIF Receiver ......................................................43
SPI Interface—Slave .................................................45
Rev. D | Page 2 of 56 | April 2013



Analog Devices ADSP-21375
GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC® processors are mem-
bers of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x, and
ADSP-2116x DSPs, as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point proces-
sors optimized for high performance automotive audio
applications with their large on-chip SRAM and mask-pro-
grammable ROM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital applications interface
(DAI).
As shown in the functional block diagram on Page 1, the pro-
cessors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processors achieve an instruction
cycle time of 3.75 ns at 266 MHz. With its SIMD computational
hardware, the processors can perform 1.596 GFLOPS running
at 266 MHz.
Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.
Table 1. Processor Benchmarks (at 266 MHz)
Benchmark Algorithm
Speed
(at 266 MHz)
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 s
FIR Filter (per Tap)1
1.88 ns
IIR Filter (per Biquad)1
7.5 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
16.91 ns
30.07 ns
Divide (y/x)
13.1 ns
Inverse Square Root
20.4 ns
1 Assumes two files in multichannel SIMD mode
Table 2. ADSP-21371/ADSP-21375 Features
Feature
Frequency
RAM
ROM
Pulse-Width Modulation
Serial Ports
UART
Digital Application
Interface (DAI)
ADSP-21371 ADSP-21375
266 MHz
(3.75 ns)
266 MHz
(3.75 ns)
1M bit
0.5M bit
4M bits
2M bits
Yes No
84
1
Yes
ADSP-21371/ADSP-21375
Table 2. ADSP-21371/ADSP-21375 Features (Continued)
Feature
ADSP-21371 ADSP-21375
Digital Peripheral Interface
(DPI)
Yes
S/PDIF Transceiver
Yes
No
SPI 2
TWI Yes
Package
208-Lead LQFP_EP
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2137x processors. The core clock domain contains
the following features:
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
ADSP-21375)
• On-chip mask-programmable ROM (4M bit, ADSP-21371;
2M bit, ADSP-21375)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allow flexible exception handling.
The diagram on Page 1 also shows the peripheral clock domains
(also known as the I/O processor) and contains the following
features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port bus for core connection
• Digital applications interface that includes four precision
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter, an input data port (IDP), eight
serial ports, eight serial interfaces, a 20-bit parallel input
port (PDAP), and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
• External port with AMI and SDRAM controller
• Four units for PWM control
• One MTM for internal to internal memory transfers
Rev. D | Page 3 of 56 | April 2013







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