ADSP-21375 Processor Datasheet

ADSP-21375 Datasheet, PDF, Equivalent


Part Number

ADSP-21375

Description

SHARC Processor

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download ADSP-21375 Datasheet


ADSP-21375
SHARC Processor
ADSP-21371/ADSP-21375
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Order-
ing Guide on Page 56.
DEDICATED AUDIO COMPONENTS
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 33 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in a 208-lead LQFP_EP package
SIMD Core
Instruction
Cache
5 stage
Sequencer
DAG1/2
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
S
DMD 64-BIT
PMD 64-BIT
Core Bus
Cross Bar
DMD 64-BIT
PMD 64-BIT
PERIPHERAL BUS
32-BIT
EPD BUS 48-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
Internal Memory I/F
IODO 32-BIT
IOD1
32-BIT
PERIPHERAL BUS
IOD0 BUS
MTM/
D TCP
EP
CORE PCG TIMER
FLAGS C-D
1-0 TWI SPI/B UART
PCG S/PDIF IDP/ SPORT
A-D Tx/Rx PDAP 7-0
7-0
CORE PWM
FLAGS 3-0
AMI SDRAM
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

ADSP-21375
ADSP-21371/ADSP-21375
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 6
I/O Processor Features ......................................... 10
System Design .................................................... 10
Development Tools ............................................. 11
Additional Information ........................................ 12
Related Signal Chains .......................................... 12
Pin Function Descriptions ....................................... 13
ADSP-21371/ADSP-21375 Specifications .................... 16
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 17
Package Information ............................................ 18
Maximum Power Dissipation ................................. 18
Absolute Maximum Ratings ................................... 18
ESD Sensitivity ................................................... 18
Timing Specifications ........................................... 18
Output Drive Currents ......................................... 49
Test Conditions .................................................. 49
Capacitive Loading .............................................. 49
Thermal Characteristics ........................................ 50
208-Lead LQFP_EP Pinout ....................................... 51
Package Dimensions ............................................... 55
Automotive Products .............................................. 56
Ordering Guide ..................................................... 56
REVISION HISTORY
4/13—Rev. C to Rev. D
Corrected Extended Precision Normal or Instruction Word
(48 bits) ADSP-21375 Internal Memory Space .................7
Updated Development Tools ..................................... 11
Added section Related Signal Chains ...........................12
Revised MS1-0 pin description in
Pin Function Descriptions ........................................ 13
Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in
Pin Function Descriptions ........................................ 13
Corrected TJUNCTION specifications in
Operating Conditions .............................................. 16
Added footnote 3 to Table 25 in
Memory Read—Bus Master ....................................... 29
Updated Serial Ports timing parameter data in Serial Ports—
External Clock ....................................................... 33
Updated Serial Ports timing parameter data in Serial Ports—
Internal Clock ........................................................ 34
Changed Max values in Table 33 in Pulse-Width Modulation
Generators (PWM) ................................................. 40
Updated timing parameters in Table 37 and in Figure 31 in
SPI Interface—Master .............................................. 44
Added 1.0 V, 200 MHz specifications to the following timing
specifications.
Clock Input ............................................................21
Precision Clock Generator (Direct Pin Routing) .............26
SDRAM Interface Timing ..........................................28
Memory Read—Bus Master .......................................29
Memory Write—Bus Master ......................................31
Serial Ports ............................................................33
Input Data Port (IDP) ..............................................38
S/PDIF Transmitter Input Data Timing ........................42
S/PDIF Receiver ......................................................43
SPI Interface—Slave .................................................45
Rev. D | Page 2 of 56 | April 2013


Features SHARC Processor ADSP-21371/ADSP-21375 S UMMARY High performance 32-bit/40-bit f loating point processor optimized for h igh performance audio processing Single -instruction, multiple-data (SIMD) comp utational architecture On-chip memory, ADSP-21371—1M bits of on-chip SRAM an d 4M bits of on-chip mask-programmable ROM On-chip memory, ADSP-21375—0.5M b its of on-chip SRAM and 2M bits of on-c hip mask-programmable ROM Code compatib le with all other members of the SHARC family The ADSP-21371/ADSP-21375 proces sors are available with a 200/266 MHz c ore instruction rate with unique audioc entric peripherals such as the digital applications interface, S/PDIF transcei ver, serial ports, precision clock gene rators, and more. For complete ordering information, see Ordering Guide on Pag e 56. DEDICATED AUDIO COMPONENTS ADSP- 21371—S/PDIF-compatible digital audio receiver/transmitter ADSP-21371—8 du al data line serial ports that operate at up to 33 Mbps on each data line — each has a clock, frame sync, and .
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