HSTL16918

www.DataSheet4U.com INTEGRATED CIRCUITS HSTL16918 9-bit to 18-bit HSTL-to-LVTTL memory address latch Product data 2001 Jun 16 Philips Semiconductors Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 FEATURES Inputs meet JEDEC HSTL Std. JESD 8–6, and outputs meet Level III specifications PIN CONFIGURATION 2Q1 1Q1 GND D1 D2 VCC D3 1 2 3 4 5 6 7 8 9 48 VCC 47 VCC 46 1Q2 45 2Q2 44 GND 43 1Q3 42 2Q3 41 VCC 40 1Q4 39 2Q4 38 GND 37 1Q5 36 2Q5 35 GND 34 1Q6 33 2Q6 32 VCC 31 1Q7 30 2Q7 29 GND 28 1Q8 27 2Q8 26 VCC 25 VCC ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. Packaged in 48-pin plastic thin shrink small outline package (TSSOP48) DESCRIPTION The HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input. Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is LOW the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken HIGH, the Q outputs are latched at the levels set up at the D inputs. The HSTL16918 is characterized ...