CML Comparators. ADCMP607 Datasheet

ADCMP607 Comparators. Datasheet pdf. Equivalent


Analog Devices ADCMP607
Data Sheet
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply CML Comparators
ADCMP606/ADCMP607
FEATURES
Fully specified rail to rail at VCCI = 2.5 V to 5.5 V
Input common-mode voltage from −0.2 V to VCCI + 0.2 V
CML-compatible output stage
1.25 ns propagation delay
50 mW at 2.5 V power supply
Shutdown pin
Single-pin control for programmable hysteresis and latch
(ADCMP607 only)
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
GENERAL DESCRIPTION
The ADCMP606 and ADCMP607 are very fast comparators
fabricated on XFCB2, an Analog Devices, Inc., proprietary
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from VEE − 0.5 V to
VCCI + 0.2 V, low noise, CML-compatible output drivers, and
TTL-/CMOS-compatible latch inputs with adjustable hysteresis
and/or shutdown inputs.
The devices offer 1.25 ns propagation delay with 2.5 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +2.7 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.7 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to
support a wide input signal range with independent output
swing control and power savings.
The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, latch and programmable hysteresis features are
also provided with a unique single-pin control option.
The ADCMP606 is available in a 6-lead SC70 package and the
ADCMP607 is available in a 12-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
VCCI
VCCO
(ADCMP607 ONLY)
VP NONINVERTING
INPUT
VN INVERTING
INPUT
ADCMP606/
ADCMP607
CML
Q OUTPUT
Q OUTPUT
LE/HYS INPUT (ADCMP607 ONLY)
SDN INPUT (ADCMP607 ONLY)
Figure 1.
Rev. C
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ADCMP607 Datasheet
Recommendation ADCMP607 Datasheet
Part ADCMP607
Description Single-Supply CML Comparators
Feature ADCMP607; www.DataSheet4U.com Preliminary Technical Data FEATURES Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, S.
Manufacture Analog Devices
Datasheet
Download ADCMP607 Datasheet




Analog Devices ADCMP607
ADCMP606/ADCMP607
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Information ..................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
4/16—Rev. B to Rev. C
Changes to Figure 4 and Table 6..................................................... 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
11/14—Rev. A to Rev. B
Changes to Figure 4 and Table 6..................................................... 7
Changes to Figure 12 and Figure 13............................................... 9
Changes to Comparator Hysteresis Section................................ 11
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
8/07—Rev. 0 to Rev. A
Changes to Specifications Section.................................................. 3
Changes to Table 3............................................................................ 6
Changes to Ordering Guide .......................................................... 14
10/06—Revision 0: Initial Version
Data Sheet
Applications Information .............................................................. 10
Power/Ground Layout and Bypassing..................................... 10
CML-Compatible Output Stage ............................................... 10
Using/Disabling the Latch Feature........................................... 10
Optimizing Performance........................................................... 10
Comparator Propagation Delay Dispersion............................... 11
Comparator Hysteresis .............................................................. 11
Crossover Bias Points................................................................. 12
Minimum Input Slew Rate Requirement................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
Rev. C | Page 2 of 14



Analog Devices ADCMP607
Data Sheet
ADCMP606/ADCMP607
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = −40°C to +125°C, typical at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Voltage Range
Common-Mode Range
Differential Voltage
Offset Voltage
Bias Current
Offset Current
Capacitance
Resistance, Differential Mode
Resistance, Common Mode
Active Gain
Common-Mode Rejection Ratio
Hysteresis
LATCH ENABLE PIN CHARACTERISTICS
(ADCMP607 Only)
VIH
VIL
IIH
IIL
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage
Minimum Resistor Value
Latch Setup Time
Latch Hold Time
Latch-to-Output Delay
Latch Minimum Pulse Width
SHUTDOWN PIN CHARACTERISTICS
(ADCMP607 Only)
VIH
VIL
IIH
IIL
Sleep Time
Wake-Up Time
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
Symbol Test Conditions/Comments
VP, VN
VOS
IP, IN
VCCI = 2.5 V to 5.5 V
VCCI = 2.5 V to 5.5 V
VCCI = 2.5 V to 5.5 V
CP, CN
AV
CMRR
−0.1 V to VCCI
−0.5 V to VCCI + 0.5 V
VCCI = 2.5 V, VCCO = 2.5 V,
VCM = −0.2 V to +2.7 V
VCCI = 2..5 V, VCCO = 5.5 V
RHYS = ∞
Hysteresis is shut off
Latch mode guaranteed
VIH = VCCO
VIL = 0.4 V
tS
tH
tPLOH, tPLOL
tPL
Current sink 0 µA
Hysteresis = 120 mV
VOD = 50 mV
VOD = 50 mV
VOD = 50 mV
VOD = 50 mV
Comparator is operating
Shutdown guaranteed
VIH = VCCO
VIL = 0 V
tSD 10% output swing
tH VOD = 100 mV, output valid
VCCO = 2.5 V to 5.5 V
VOH 50 Ω terminate to VCCO
VOL 50 Ω terminate to VCCO
50 Ω terminate to VCCO
Min
−0.5
−0.2
−5.0
−5.0
−2.0
200
100
50
50
2.0
−0.2
−6
−0.1
1.145
55
2.0
−0.2
−6
VCCO − 0.1
VCCO − 0.6
300
Typ
±2
1
700
350
85
<0.1
+0.4
1.25
75
−1.5
2.3
30
25
+0.4
<1
35
VCCO − 0.05
VCCO − 0.45
400
Max
VCCI + 0.2
VCCI + 0.2
VCCI
+5.0
+5.0
2.0
VCCO
+0.8
+6
+0.1
1.35
110
VCCO
+0.6
+6
−0.1
VCCO
VCCO − 0.3
500
Unit
V
V
V
mV
µA
µA
pF
kΩ
kΩ
dB
dB
dB
mV
V
V
µA
mA
V
kΩ
ns
ns
ns
ns
V
V
µA
mA
ns
ns
V
V
mV
Rev. C | Page 3 of 14







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