NB4N11M

3.3 V, 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/Buffer/Translator NB4N11M Description The NB4N11M is a differential 1−to−2 clock/data distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device produces two identical differential output copies of clock or data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 5). The CML outputs are 16 mA open collector (See Figure 18) which requires resistor (RL) load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. Differential outputs produces current–mode logic (CML) compatible levels when receiver loaded with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies (see Figure 19). This simplifies device interface by eliminating a need for coupling capacitors. The device is offered in a small 8−pin TSSOP package. Application notes, models, and support documentation are available at www.onsemi.com. Features Maximum Input Clock Frequency > 2.5 GHz Maximum Input Data Rate > 2.5 Gb/s Typically 1 ps of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 W 420 ps Typical Propagation Delay 150 ps Typical Rise and Fall Ti...