NB6L611

NB6L611 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer Multi−Level Inputs with Internal Termination http://onsemi.com Description The NB6L611 is a differential 1:2 clock or data fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VREFAC output should be left open. The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L611 is a member of the ECLinPS MAX™ family of high performance clock and data management products. Features Input Clock Frequency > 4.0 GHz 280 ps Typical Propagation Delay 100 ps Typical Rise and Fall Times 0.5 ps maximum RMS Clock Jitter Differential LVPECL Outputs, 780 mV Amplitude, typical LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V NECL Operating Range: VCC = 0 V with VEE = −2.375 V to −3.63 V Internal Input Termination Resistors, 50 W VREFAC Reference Output Voltage Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices MARKI...