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GPS Receiver. ATR0630 Datasheet |
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Features
• 16-channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (2D, Stand Alone)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –139 dBm (With External LNA)
– Tracking Sensitivity: –149 dBm (With External LNA)
• Utilizes the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– Embedded ICE (In-Circuit Emulation)
• 128 Kbytes Internal RAM
• 384 Kbytes Internal ROM with u-blox GPS Firmware
• 1.5-bit ADC On-chip
• Single IF Architecture
• 2 External Interrupts
• 24 User-programmable I/O Lines
• 1 USB Device Port
– Universal Serial Bus (USB) 2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
• 2 USARTs
• Master/Slave SPI Interface
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Advanced Power Management Controller (APMC)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
• Real Time Clock (RTC)
• 1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance
• 4 KBytes of Battery Backup Memory
• 7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
Benefits
• Fully Integrated Design With Low BOM
• No External Flash Memory Required
• Requires Only a GPS XTAL, No TCXO
• Supports NMEA, UBX Binary and RTCM Protocol
• Supports SBAS (WAAS, EGNOS, MSAS)
• Up to 4Hz Update Rate
• Supports A-GPS (Aiding)
• Excellent Noise Performance
ANTARIS4
Single-chip
GPS Receiver
ATR0630
Preliminary
Rev. 4920A–GPS–01/06
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1. Description
The ATR0630 is a low-power, single-chip GPS receiver, especially designed to meet the
requirements of mobile applications. It is based on Atmel’s ANTARIS™4 technology and inte-
grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm × 10 mm
96 pin BGA package. Providing excellent RF performance with low noise figure and low power
consumption.
Due to the fully integrated design, just an RF SAW filter, a GPS XTAL (no TCXO) and blocking
capacitors are required to realize a stand-alone GPS functionality.
The ATR0630 includes a complete GPS firmware, licensed from u-blox AG, which performs the
GPS operation, including tracking, acquisition, navigation and position data output. For normal
PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory.
The firmware supports the possibility to store the configuration settings in an optional external
EEPROM.
Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the ATR0630
operates in a complete autonomous mode, utilizing on chip AGC in closed loop operation.
For maximum performance, we recommend to use the ATR0630 together with a low noise
amplifier (e.g. ATR0610).
The ATR0630 supports assisted GPS.
2 ATR0630 [Preliminary]
4920A–GPS–01/06
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2. Architectural Overview
2.1 Block Diagram
Figure 2-1. ATR0630 Block Diagram
PUXTO
PURF
VDD18
VDDIO
VDD_USB
VDIG
VCC1
VCC2
VBP
TEST
MO
RF
NRF
XTO
NXTO
X
NX
RF_ON
NSHDN
NSLEEP
XT_IN
XT_OUT
P20/TIMEPULSE
P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10
P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2
P1/GPSMODE0
P14/NAADET1
P25/NAADET0
P15/ANTON
P0/NANTSHORT
P9/EXTINT0
P16/NEEPROM
VCO
PLL
XTO
ATR0630 [Preliminary]
Power Supply Manager/
PMSS/Logic
1
A
D
A
D
VBAT18
VBAT
LDOBAT_IN
LDO_OUT
LDO_IN
LDO_EN
AGCO
EGC
SDI
SIGHI
SIGLO
CLK23
P21/TXD2
P22/RXD2
P18/TXD1
P31/RXD1
USB_DP
USB_DM
P8/STATUSLED
P30/AGCOUT0
P2/BOOT_MODE
4920A–GPS–01/06
DBG_EN
NTRST
TDI
TDO
TCK
TMS
NRESET
3
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