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Transceiver IC. ADN2928 Datasheet |
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Preliminary Technical Data
FEATURES
Fully integrated limiting amplifier and signal conditioner
transceiver IC
Meets XFP Telecoms and Datacoms module requirements
Supports OC-192, OC-192-FEC, 10GE, 10GFC, 10GE G.709
Line and system loop-back modes
Integrated Rx limiting amplifier with 10 mV sensitivity
Tx path equalizer for up to 12 inches of FR4
Rx loss of signal (LOS) detector
CML serial data interface
Supply power: 760 mW
3.3 V and 1.8 V power supplies
XFI signalling
Flip-chip, 49-pin BGA, 6 mm × 6 mm package
Temperature range 0°C to 85°C
Power down mode
APPLICATIONS
XFP MSA module receive/transmit signal conditioner
SONET OC-192, (+FEC) transponders
10 gigabit Ethernet optical transceivers
10 gigabit small form factor modules
Test equipment
Serial backplane applications
12” FR4
TXDATA
XFP MODULE
OTX
SERDES/
ASIC
ADN2928
12” FR4
RXDATA
ORX
XFP Single Chip Transceiver IC
ADN2928
PRODUCT OVERVIEW
The ADN2928 provides the transmit and receive functions of
quantization, loss of signal detect, and clock and data recovery
at rates from 9.953 Gbps to 11.1 Gbps. The part is designed with
the flexibility to allow it to be used in either Telecoms or
Datacoms XFP module applications. The key advantages of this
circuit’s delay and phase-locked loop architecture are that it
provides a low jitter transfer bandwidth of 1 MHz, while also
exceeding the jitter tolerance requirements of XFP, SONET,
Gigabit Ethernet and Fibre Channel. The architecture also
provides fundamentally 0 dB of Jitter peaking.
XFP MODULE
ORX
12” FR4
RXDATA
ADN2928
SERDES/
ASIC
OTX
12” FR4
TXDATA
Figure 1. Typical XFP Application
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
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ADN2928
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
Receive Path Specifications ............................................................. 4
Transmit Path Specifications........................................................... 5
Common Specifications................................................................... 6
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Function Descriptions............................. 8
General Description ......................................................................... 9
I2C Interface .................................................................................. 9
Receive Path .................................................................................. 9
Transmit Path................................................................................ 9
System Functions.......................................................................... 9
Applications Information .............................................................. 10
PCB Design Guidelines ............................................................. 10
Outline Dimensions ....................................................................... 11
Ordering Guide........................................................................... 11
REVISION HISTORY
3/05—Revision PrB: Preliminary Version
Preliminary Technical Data
Rev. PrB | Page 2 of 12
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Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
ADN2928
T xOU T P
T xOU T N
RxL OS
RxT H R
RxIN P
RxIN N
COSR
Limiting Amp
VD D T _1.8
VD D R_1.8
VD D _3.3
GN D
CFT
T xL OL
FL L
T xCD R
Equalizer
44
1.0V
regulator
RxCD R
FL L
T xL OL
RxL OL
I2C
REGI ST ERS
CVD D _1.0
CFR
Figure 2. ADN2928 Functional Block Diagram
T xI N P
T xIN N
COST
REFCK P
REFCK N
RxOU T P
RxOU T N
CD R_N R
SCK
SD A
PD N
Rev. PrB | Page 3 of 12
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