DatasheetsPDF.com

DS3184 Dataheets PDF



Part Number DS3184
Manufacturers Maxim Integrated Products
Logo Maxim Integrated Products
Description (DS3181 - DS3184) Single/Dual/Triple/Quad ATM/Packet PHYs
Datasheet DS3184 DatasheetDS3184 Datasheet (PDF)

www.DataSheet4U.com DS3181/DS3182/DS3183/DS3184 Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU www.maxim-ic.com GENERAL DESCRIPTION The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate ATM cell/HDLC packet processor(s) with a DS3/E3 framer(s) and LIU(s) to map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed, E3-framed, or clear-channel data streams on per-port basis. FUNCTIONAL DIAGRAM DS3/E3/STS-1 LIU DS3/E3/STS-1 PORTS APPLICAT.

  DS3184   DS3184


Document
www.DataSheet4U.com DS3181/DS3182/DS3183/DS3184 Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU www.maxim-ic.com GENERAL DESCRIPTION The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate ATM cell/HDLC packet processor(s) with a DS3/E3 framer(s) and LIU(s) to map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed, E3-framed, or clear-channel data streams on per-port basis. FUNCTIONAL DIAGRAM DS3/E3/STS-1 LIU DS3/E3/STS-1 PORTS APPLICATIONS Access Concentrators SONET/SDH ADM SONET/SDH Muxes PBXs Digital Cross Connect Test Equipment Routers and Switches Integrated Access Device (IAD) Multiservice Access Platform (MSAP) Multiservice Protocol Platform (MSPP) ATM and Frame Relay Equipment PDH Multiplexer/ Demultiplexer CELL/ DS3/E3 PACKET FRAMER/ FORMATTER PROCESSOR SYSTEM INTERFACE POS-PHY OR UTOPIA DS318x FEATURES § Single (DS3181), Dual (DS3182), Triple (DS3183), or Quad (DS3184) with Integrated LIU ATM/Packet PHYs for DS3, E3, and ClearChannel 52Mbps (CC52) Pin Compatible for Ease of Port Density Migration in the Same PC Board Platform Each Port Independently Configurable Perform Receive Clock/Data Recovery and Transmit Waveshaping Jitter Attenuator can be Placed Either in the Receive or Transmit Paths Interfaces to 75W Coaxial Cable at Lengths Up to 380 Meters or 1246 Feet (DS3) or 440 Meters or 1443 Feet (E3) Uses 1:2 Transformers on Both Tx and Rx Universal PHYs Map ATM Cells and/or HDLC Packets into DS3 or E3 Data Streams UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width 66MHz UTOPIA L3 and POS-PHY L3 Clock 52MHz UTOPIA L2 and POS-PHY L2 Clock Ports Independently Configurable for Cell or Packet Traffic in POS-PHY Bus Modes Direct, PLCP, DSS, and Clear-Channel Cell Mapping ORDERING INFORMATION PART DS3181* DS3181N* DS3182* DS3182N* DS3183* DS3183N* DS3184 DS3184N TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C PIN-PACKAGE 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) § § § § § § § § § § § § *Future product—contact factory for availability. POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 389 REV: 061604 DS3181/DS3182/DS3183/DS3184 FEATURES (continued) § § § § § § Direct and Clear-Channel Packet Mapping On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or G.832) Framer(s) Ports Independently Configurable for DS3, E3 (Full or Subrate) or Arbitrary Framing Protocols Up to 52Mbps Programmable (Externally Controlled or Internally Finite State Machine Controlled) Subrate DS3/E3 Full-Featured DS3/E3/PLCP Alarm Generation and Detection Built-In HDLC Controllers with 256-Byte FIFOs for Insertion/Extraction of DS3 PMDL, G.751 Sn Bit, and G.832 NR/GC Bytes and PLCP NR/GC Bytes On-Chip BERTs for PRBS and Repetitive Pattern Generation, Detection, and Analysis Large Performance-Monitoring Counters for Accumulation Intervals of at Least 1 Second Flexible Overhead Insertion/Extraction Ports for DS3, E3, and PLCP Framers § Loopbacks Include Line, Diagnostic, Framer, Payload, Analog, and System Interface with Capabilities to Insert AIS in the Directions Away from Loopback Directions Ports can be Disabled to Reduce Power Integrated Clock Rate Adapter to Generate the Remaining Internally Required 44.736MHz (DS3), 34.368MHz (E3), and 52MHz (Arbitrary Framing at Up to 52Mbps) from a Single Clock Reference Source at One of Those Three Frequencies Pin Compatible with the DS3171/2/3/4 Family and the DS3161/2/3/4 Family 8/16-Bit Generic Microprocessor Interface Low-Power (2.7W typ) 3.3V Operation (5VTolerant I/O) Small, High-Density, Thermally Enhanced, ChipScale BGA Packaging (TE-CSBGA) with 1.27mm Pin Pitch Industrial Temperature Operation: -40°C to +85°C IEEE1149.1 JTAG Test Port § § § § § § § § § § § DETAILED DESCRIPTION The DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs perform all the functions necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3 (34.368Mbps) framed, or 52Mbps clear-channel data streams on DS3, E3, or STS-1 physical copper lines. Each line interface unit (LIU) has independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal or can be bypassed for direct clock and data .


DS3183 DS3184 DS90LV028AH


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)